【正文】 or negative: for positive numbers S = 0 and for negative numbers S = 1. If the DS18B20 is configured for 12bit resolution, all bits in the temperature register will contain valid data. For 11bit resolution, bit 0 is undefined. For 10bit resolution, bits 1 and 0 are undefined, and for 9bit resolution bits 2, 1, and 0 are undefined. Table 1 gives examples of digital output data and the corresponding temperature reading for 12bit resolution conversions. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 LS Byte 23 22 21 20 21 22 23 24 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MS Byte S S S S S 26 25 24 Figure Register Format TEMPERATURE DIGITAL OUTPUT (BINARY) DIGITAL OUTPUT (HEX) +125℃ 0000 0111 1101 0000 07D0H +℃ 0000 0001 1001 0001 0191H 0℃ 0000 0000 0000 0000 0000H ℃ 1111 1110 0110 1111 FE6FH 55℃ 1111 1100 1001 0000 FC90H Table LASERED ROM CODE 外文翻譯（原文） 5 Each DS18B20 contains a unique 64–bit code (see Figure 3) stored in ROM. The least significant 8 bits of the ROM code contain the DS18B20’s 1Wire family code: 28h. The next 48 bits contain a unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated from the first 56 bits of the ROM code. The 64bit ROM code and associated ROM function control logic allow the DS18B20 to operate as a 1Wire device using the protocol detailed in the 1Wire Bus System section. 8BIT CRC 48BIT SERIAL NUMBER 8BIT FAMILY CODE MSB LSB MSB LSB MSB Figure Lasered ROM Code The DS18B20’s memory is anized as shown in Figure 4. The memory consists of an SRAM scratchpad with nonvolatile EEPROM storage for the hi gh and low alarm trigger registers (TH and TL) and configuration register. Note that if the DS18B20 alarm function is not used, the TH and TL registers can serve as generalpurpose memory. Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register, respectively. These bytes are readonly. Bytes 2 and 3 provide access to TH and TL registers. Byte 4 contains the configuration register data. Bytes 5, 6, and 7 are reserved for internal use by the device and cannot be overwritten. Byte 8 of the scratchpad is readonly and contains the CRC code for bytes 0 through 7 of the scratchpad. The DS18B20 generates this CRC using the method described in the CRC Generation section. Data is written to bytes 2, 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] mand。 the data must be transmitted to the DS18B20 starting with the least significant bit of byte 2. To verify data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] mand) after the data is written. When reading the scratchpad, data is transferred over the 1Wire bus starting with the least significant 外文翻譯（原文） 6 bit of byte 0. To transfer the TH, TL and configuration data from the scratchpad to EEPROM, the master must issue the Copy Scratchpad [48h] mand. Byte0 Temperature LSB Byte1 Temperature MSB Byte2 TH Register for high temperature Byte3 TL Register for low temperature Byte4 Configuration Register Byte5 Reserved（ FFH） Byte6 Reserved（ OCH） Byte7 Reserved（ IOH） Byte8 Cyclic Redundancy Checks（ CRC） Figure Memory Map REGISTER Byte 4 of the scratchpad memory contains the configuration register, which is anized as illustrated in Figure 5. The user can set the conversion resolution of the DS18B20 using the R0 and R1 bits in this register as shown in Table 2. The powerup default of these bits is R0 = 1 and R1 = 1 (12bit resolution). Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0 to 4 in the configuration register are reserved for internal use by the device and cannot be overwritten. BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 TM R1 R0 1 1 1 1 1 Figure Register R0 R1 RESOLUTION(BITS) MAX CONVERSION TIME 外文翻譯（原文） 7 Table Resolution Configuration BUS SYSTEM The 1Wire bus system uses a single bus master to control one or more slave devices. The DS18B20 is always a slave. When there is only one slave on the bus, the system is referred to as a ―singledrop‖ system。 the system is ―multidrop‖ if there are multiple slaves on the bus. All data and mands are transmitted least significant bit first over the 1Wire bus. The following discussion of the 1Wire bus system is broken down into three topics: hardware configuration, transaction sequence, and 1Wire signaling (signal types and timing). SEQUENCE The transaction sequence for accessing the DS18B20 is as follows: Step 1. Initialization Step 2. ROM Command (followed by any required data exchange) Step 3. DS18B20 Function Command (followed by any required data exchange) It is very important to follow this sequence every time the DS18B20 is accessed, as the DS18B20 will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [F0h] and Alarm Search [ECh] mands. After issuing either of these ROM mands, the master must return to Step 1 in the sequence. （ 1） INITIALIZATION All transactions on the 1Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed 0 0 1 1 0 1 0 1 9 10 11 12 375ms 750ms 外文翻譯（原文） 8 by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18B20) are on the bus and are ready to operate. （ 2） ROM COMMANDS After the bus master has detected a presence pulse, it can issue a ROM mand. These mands operate on the unique 64bit ROM codes of each slave de