【正文】 n consists of a ROM to provide storage of the twiddle factor matrix nW , another ROM to control the addressing of the twiddle factors for a particular qw and 4 registers which continuously recirculate the filter parameter results( na? )from the Cholesky deposition stage. On interleave 6 the real and imaginary parts of the first set of products 1?aWiN? are alternately formed. Using a single flipflop delay the results of these putations are then fed back into the iZ input of the interleaved processor to be added to the products 2?aWiN? and the DFT is built up in this way. The dynamicrange of the PSD putation is quite high pared to the rest of the system, therefore, at this stage a floating point representation of the DFT results is taken using a systolic based conversion circuit. PIPO registers are used to store the 6 bit exponents of the real and imaginary parts of the DFT, whose squares are puted on interleave 10. On interleave 11 the absolute value of the DFT is puted. The maximum of each pair of real and imaginary results from interleave 10 is fed to the iZ input while the other value is piped into the iY to be appropriately scaled by the difference in the two squared exponents appearing on the iX input. The PSD is then puted on interleave 12, involving N/2 divisions of the WNV formed on interleave 5 with the absolute values from interleave 11. The exponents of the PSD are then easily derived from the exponents of the DFT results. 5. CONCLUSION This paper has proposed a bitserial interleaved processor which can be programmed for use in division or inner product step putations. The interleaving idea was introduced in order to perform bitserial division at the same high clock rate as multiplication without resorting to carry lookahead schemes to remove the munication bottleneck. The result is a high throughput processor which is cost ef?cient in terms of VLSI implementation, since munication between PEs in the linear array is localised and control is very simple. An application in parametric spectral estimation, namely implementation of theModi?ed Covariance spectral estimator, which makes full use of the interleaving scheme, was described. This system has been programmed and simulated using VHDL. Synthesis was targeted to exploit the resources of a Xilinx XC4036EX2 FPGA. This type of FPGA has dual port RAM capability, where a 16x1 bit dual port RAM can be implemented in a single con?gurable logic block (CLB). A dual port RAM cell is an area ef?cient method to implement a 13 or 14 bit SISO register, as used in the interleaving process. Such registers would otherwise have to be implemented using the pairs of ?ip?ops in each CLB, CLBs. CLBs can also be con?gured as ROM blocks which are useful for generating the address signals in the Cholesky and PSD modules, and for storage of the DFT twiddle factors. The processor design exhibits mostly localised munication to make use of the fast routing resources between nearest neighbours in the FPGA’s CLB matrix and enable high speed operation. Timing analysis of the FPGA layout shows that the maximum processor clock frequency of 35MHz allows realtime spectral estimation to be performed for the speci?ed constraints. The reprogrammable aspect of the FPGA is also useful。 rather than designing control logic to switch between the different values of N, which uses resources and is likely to slow clock speed, a different bitstream can be downloaded for each N. This idea can also be extended for changing to higher model order estimations where otherwise it would be dif?cult to paramete rise p in such a system. 6. REFERENCES [1] S. M. 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Fleming, “ Alternative parallel implementationsof an ARmodi?ed covariance spectral estimator for diagnostic ultrasound blood ?ow studies, ” Parallel Computing, vol. 19, no. 4, pp. 463476, 1993. [7] S. J. Bellis, P. J. Fish, and W. P. Marnane, “Optimal systolic arrays for realtime implementation of the Modi?ed Covariance spectral estimator, ”P(pán)arallel Algorithms and Applications, vol .11, no. 12, pp. 71–96, 1997. [8] S. J. Bellis, W. P. Marnane, and P. J. Fish, “Alternative systolic array for nonsquareroot Cholesky deposition, ”IEE Proceedings: Computers and Digital Techniques, vol. 144, pp. 57–64, Mar. 1997. [9] K. Hwang, Computer Arithmetic: Principles Architecture and Design. John Wiley amp。 Sons, 1979. 中文譯文 單一 FPGA 上 的參數(shù)譜估計(jì) 摘要 參數(shù)化譜估計(jì)模型技術(shù) 可以提供 針對(duì) 傳統(tǒng)的短期快速傅里葉變換 提高 頻率分辨率的方法 ， 克服了窗口 采樣， 時(shí)域，輸入 數(shù)據(jù) 造成的限制 。然而， 參數(shù) 化技術(shù)相比于 傅立葉 變換 具有更高的要求， 它 需要更廣泛的算術(shù)功能 ， 例如 一些 操作 ,如 除法 和 平方根運(yùn)算， 通常是必要的 。這些算術(shù)過(guò)程演示通信瓶頸和其硬件實(shí)現(xiàn)在連同乘法器使用時(shí)是低效能的?？沙淌娇刂疲淮?，乘法器 /除法器，它們使用了一個(gè)數(shù)據(jù)交錯(cuò)方案，克服了瓶頸問(wèn)題。本文中會(huì)有所介紹。這個(gè)交錯(cuò)處理器是用來(lái)顯示參數(shù)化修正協(xié)方差譜估計(jì)如何有效地按路線 發(fā)送到實(shí)時(shí)應(yīng)用的現(xiàn)場(chǎng)可編程門(mén)陣列。 1. 引言 由于其硬件和軟件實(shí)現(xiàn) 簡(jiǎn)單，因此短 期的快速傅里葉變換 (STFFT)被廣泛用于譜估計(jì) ，并 被 認(rèn)為是 常規(guī)方法 。 然而 ， 該技術(shù) 因?yàn)檩斎霐?shù)據(jù)的序列長(zhǎng)度有限因此對(duì) 譜分辨率和有限長(zhǎng)度的準(zhǔn)確性方面 造成 缺陷 ，輸入數(shù)據(jù)的窗函數(shù)會(huì)導(dǎo)致光譜擴(kuò)展和吉布的頻譜泄漏現(xiàn)象，掩蓋了真正的功率譜密度較弱的頻率成分（ PSD） [1]。這些不良效應(yīng)，可通過(guò)使用更長(zhǎng)長(zhǎng)度的數(shù)