外文翻譯---關于直接數(shù)字頻率合成器-其他專業(yè)(已改無錯字)
2023-03-03 09:22:33 本頁面
【正文】 n Cout fMf 2?? where: fOUT = output frequency of the DDS M = binary tuning word fC = internal reference clock frequency (system clock) n = length of the phase accumulator, in bits Changes to the value of M result in immediate and phasecontinuous changes in the output frequency. No loop settling time is incurred as in the case of a phaselocked loop. As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the phase accumulator increases 5 linearly, so the analog waveform it generates is inherently a ramp. Then how is that linear output translated into a sine wave? A phase to amplitude lookup table is used to convert the phaseaccumulator’s instantaneous output value (28 bits for AD9833)— with unneeded lesssignificant bits eliminated by truncation— into the sinewave amplitude information that is presented to the (10 bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a plete sine wave from onequartercycle of data from the phase accumulator. The phaseto amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5. Figure 5. Signal flow through the DDS architecture. 6 關于直接數(shù)字頻率合成器 什么是直接數(shù)字頻率合成器？ 直接數(shù)字頻率合成器（ DDS）是一種通過產生一個以數(shù)字形式時變的信號，然后執(zhí)行由數(shù)字至模擬轉換的方法。由于 DDS 設備的操作主要是數(shù)字的，它可以提供快速解決輸出頻率之間切換， 優(yōu)點是具有 精細的頻率 以及 運行頻率范圍廣泛。由于設計 方面 和工藝技術的進步， 如今 DDS 器件 已變得 非常緊湊 而且功率非常小。 為什么要使用直接數(shù)字頻率合成器（ DDS）？ 難道沒有其它方法使 不同頻率和配置文件 能夠 很容易 地 產生頻率？ 能夠準確地產生和控制波形已經成為一些行業(yè)的主要要求。無論 是 提供低相位噪 聲的雜散性能良好的可變頻率通信， 還是 只需在生成的頻率 上 激活工業(yè)或生物醫(yī)學檢測設備的應用程序，成本低是重要的設計考慮。 設計師以相位鎖定回路（ PLL）為基礎 ， 需要非常高的頻率合成技術，以動態(tài)規(guī)劃的數(shù)字 到模擬的 轉換器（ DAC） 來產生 許多可能產生 的 頻率，但 DDS 技術迅速獲得 了解決頻率（或波形）
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