外文翻譯-關(guān)于直接數(shù)字頻率合成器-其他專業(yè)(已改無(wú)錯(cuò)字)
2023-03-03 00:33:56 本頁(yè)面
【正文】 ications. The advantages that make them attractive to design engineers include: ? digitally controlled microhertz frequencytuning and subdegree phasetuning capability, ? extremely fast hopping speed in tuning output frequency (or phase)。 phase continuous frequency hops with no overshoot/undershoot or analogrelated loop settlingtime anomalies, ? the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to ponent aging and temperature drift in analog synthesizer solutions, and ? the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution 外文翻譯（原文） 8 under processor control. What are the key performance specs of a DDS based system? Phase noise, jitter, and spuriousfree dynamic range (SFDR). Phase noise is a measure (dBc/Hz) of the shortterm frequency instability of the oscillator. It is measured as the singlesideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog munications industry. Do DDS devices have good phase noise? Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS system。 and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binarycoded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral plot. Their magnitudes and distribution depends on the code word chosen. The DAC also contributes to noise in the system. DAC quantization or linearity errors will result in both noise and harmonics. Figure 9 shows a phase noise plot for a typical DDS device— in this case an AD9834. How can I evaluate your DDS devices? All DDS devices have an Figure 9. Typical output phase noise plot for the AD9834. Output frequency is 2 MHz and M clock is 50 MHz. 外文翻譯（原文） 9 evaluation board available for purchase. They e with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note acpanying each evaluation board contains schematic information and shows best remended boarddesign and layout practice. 西北工業(yè)大學(xué)明德學(xué)院 本科畢業(yè)設(shè)計(jì)論文 1 關(guān)于直接數(shù)字頻率 合成器 ？ 直接數(shù)字頻率合成器（ DDS）是一種通過(guò)產(chǎn)生一個(gè)以數(shù)字形式時(shí)變的信號(hào)，然后執(zhí)行由數(shù)字至模擬轉(zhuǎn)換的方法。由于 DDS 設(shè)備的 操作主要是數(shù)字的，它可以提供快速解決輸出頻率之間切換， 優(yōu)點(diǎn)是有 精細(xì)的頻率和運(yùn)行頻率范圍廣泛。由于設(shè)計(jì) 方面 和工藝技術(shù)的進(jìn)步，今天的 DDS 器件是非常緊湊的小功率。 為什么要使用直接數(shù)字頻率合成器（ DDS）？不同頻率和配置文件是不是有其他的方法 能夠 很容易 地 產(chǎn)生頻率？ 能夠準(zhǔn)確地產(chǎn)生和控制波形已經(jīng)成為一些行業(yè)的主要要求。無(wú)論 是 提供低相位噪聲的雜散性能良好的可變頻率通信， 還是 只需在生成的頻率 上 激活工業(yè)或生物醫(yī)學(xué)檢測(cè)設(shè)備的應(yīng)用程序，成本低是重要的設(shè)計(jì)考慮。 設(shè)計(jì)師以相位鎖定回路（ PLL）為基礎(chǔ)的 需要非常高的頻率 的 合成技 術(shù)，以DAC 的動(dòng)態(tài)規(guī)劃的數(shù)字 toanalog轉(zhuǎn)換器（輸出產(chǎn)生較低的頻率任意波形） 來(lái)產(chǎn)生 許多可能產(chǎn)生 的 頻率， 但 DDS 技術(shù)迅速獲得 了 解決頻率（或波形）產(chǎn)生和工業(yè)應(yīng)用要求的方法，因?yàn)閱涡酒呻娐菲骷梢援a(chǎn)生 簡(jiǎn)單的 可編程 的 模擬輸出高分辨率和準(zhǔn)確性的波形。 此外，在這兩個(gè)過(guò)程中不斷改進(jìn)技術(shù)和設(shè)計(jì)， 使 成本和功耗水平前所未有的 低 。例如 AD9833，一個(gè)基于 DDS的可編程波形發(fā)生器（圖 1）， 工作 電壓 與 25MHz的時(shí)鐘，消耗的最大功率為 30mW。 西北工業(yè)大學(xué)明德學(xué)院 本
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