【正文】 the measured signals through D Trigger output end of the counter to stop counting. And the median frequency of relevant indicators Median: At the same time the figures show that up to the median. The usual eightcount frequency of only several hundred yuan can buy. For high precision measurements, nine just beginning, the middle is 11, 13 can be relatively high. Overflow of:the ability to promote itself to overflow the equivalent of the total. Some of the frequency with overflow function, which is the highest overflow does not display only shows that the bit behind, in order to achieve the purpose of the median. Here is the estimated value of individual indicators. Speed: namely, the number of per second. With the high number of measurement particularly slow but also lose its significance. Counting of the usual eight frequency measurement 10 MHz signals, one second gate will be 10000000 Hz, which is actually seven (equivalent to the median number of mon admission after the value), to obtain eight needed 10 seconds gate 。 1 error, measurement accuracy greatly improved, and reached in the entire spectrum of measurement, such as precision measurement. In the timefrequency measurement method, the multicycle synchronization is a high precision, but still unresolved 177。 a word counting error, so as to further enhance accuracy. To measure a short time interval Δ t1 and Δ t2, monly used analog interpolation method with the cursor or more bined cycle synchronization, although accuracy is greatly improved, but eventually failed to resolve 177。 t0 for filling pulse cycle, that is 100 ns。 n2 for a short period of time at Δ t2 corresponding delay unit Number。 Delay of using quantitative measurement of the original measured not by the two short intervals, to accurately measure the size of the actual gate, it raised frequency measurement accuracy. The frequency synthesizer output frequency signal can only be transferred to the minimum 10 Hz, XDU17 as a standard of measurement can be calculated prototype frequency measurement accuracy. For example, the measured signal is measured at MHz MHz signal to , from the calculation can be seen above, the resolution of the prototype has reached ns order of magnitude below from the perspective of theoretical analysis to illustrate this point. It has been anal yzed,multicycle synchronization frequency measurement, the measurement uncertainty: When the input f0 10 MHz, 1 s gate time, the uncertainty of measurement of 177。δTx Here, δ Tx not for the accuracy of the measurement. On the decline of the share: \δTx≤177。 a theoretical error, the accuracy is increased by 20 times. CONCLUSION This paper presents a new method of measuring frequency. Based on the frequency of this method of digital integrated circuit in a CPLD, greatly reduced the volume of the entire apparatus, improved reliability, and a highresolution measurements. Frequency of VHDL Design ALTERA use of the FPGA chip EPF10K10 panies, the use of VHDL programming language design accuracy of frequency, given the core course, ISPEXPER simulation, design verification is successful, to achieve the desired results. Compared to the traditional frequency, the frequency of FPGA simplify the circuit board design, increased system design and the realization of reliability, frequency measurement range of up to 100 MHz and achieve a digital system hardware and software, which is digital logic design the new trend This design uses the AL TERA EPF10K10 FPGA chip, the chip pin the delay of 5 ns, frequency of 200 MHz, the standardization of application VHDL hardware description language has a very rich data types, the structure of the model is hierarchical, The use of these rich data types and levels of the structure model of a plex digital system logic design and puter simulation, and gradually improve after the automatic generation integrated to meet the requirements of the circuit structure of the digital logic can be realized, then can be downloaded to programmable logic devices, to plete design tasks.