【正文】 ansistor logic shaw) load. P1 interface is mon used as general I/O interface line. (4) control signal pin line A. PSEN (29 feet)。 Address latch allow/programming signals. In access to external storage, this pin is address latch signals, and about 8751 internal EPROM programming, programming the signal as pulse input. 8051 single chip microputer addressable 64 KB, 16 address thread, including low 8 address line and the data sharing P0 interface, in a low 8bit address signal, when using the ALE effective, used to control the latches latch P0 the low 8 bit address of the interface。 Input analog in the process of transformation should remain the same, if analog changes too fast, need to increase the sampling keeping circuit before input. Address input and control line: 4 ALE to address latch allow input line, the high level effectively. When the ALE line for high electricity at ordinary times, address latch and decoder will be A, B, C three address line address signal is latched, after decoding the selected channel analog transformed into the converter. A, B and C for address input line, used for gating IN0 IN7 analog input all the way. Channel selection table shown in the following table. C B A selected channel 0 0 0 IN0 0 0 1 IN1 1 0 0 IN2 0 1 1 IN3 1 0 0 IN4 1 0 1 IN5 1 1 0 IN6 1 1 1 IN7 ST for conversion start signal. When jumping along the ST, all internal registers reset。 During the period of transformation, ST should maintain a low level. EOC as the end signal conversion. When the EOC for high electricity at ordinary times, show that transformation over。 OE = 0, the output data in high impedance state. D7 D0 for digital output line. For clock CLK input signal lines. Because of ADC0809 internal clock circuit, the clock signal must be provided by the outside world, usually use frequency is 500 KHZ. VREF (+), VREF () as the reference voltage input. ADC0809 use Ⅰ . ADC0809 internal with the output latch. Ⅱ . Initialization, ST and OE signal for low level. Ⅲ . Which send to convert channel of addresses to A, B, C on port. (this design using only the first channel IN0). Ⅳ . At least 100 mu in ST side give a s wide is the pulse signal. Ⅴ . Whether conversion finished, we according to the EOC signal. Ⅵ . When the EOC is a high electricity at ordinary times, then gave OE for high level, and converting data output to the single chip microputer. a heartbeat detection principle design The pulse signal of the heart rate sensor with piezoelectric ceramic (install a sea in the piezoelectric ceramic chip pad to) pulse signals。 Through posed of diode detecting circuit, posed of three gate shaping circuit processing, microcontroller are available on the required standard of 0 to 5 v pulse signal. It received a MCU external interrupt of each interrupt a count. Every minute a show the minutes of the heart. the principle of temperature detection and design DS18B20 is introduced: DS18B20 is DALLAS semiconductor panies in the United States after the DS1820 a kind of new advanced intelligent temperature sensor. Compared with the conventional thermistor, temperature and he can read out directly according to the practical requirements through simple programming 9 ~ 12 way of digital reading. Can be done within ms and 750 ms respectively nine and 12 digital quantity, and information from DS18B20 read or written to DS18B20 information need only the mouth thread (single wire interface) to read and write, temperature transform power from the data bus, the bus itself can also supply power to the DS18B20 articulated by without additional power supply. Thus using DS18B20 can make the system more simple structure, higher reliability. He on temperature measurement accuracy, transformation time, transmission distance, resolution of the DS1820 had greatly improved, and gives the user the use of more convenient and more satisfactory effect. DS18B20 adopts 3 feet PR35 encapsulation or 8 feet SOIC package, as shown in figure 6 Figure 6 pins of DS18B20 DS18B20 internal structure is mainly posed of four parts: a 64 bit lithography ROM, temperature sensor, the temperature of the nonvolatile alarm trigger TH and TL, configuration register. ROM in a 64 bit serial number is good before delivery by lithography, it can be seen as the DS18B20 sequence of address code, each DS18B20 64 serial Numbers are not the same. 64 rows of ROM cyclic redundancy check code (CRC = by 8 + x 5 + X4 + 1). ROM role is to make every DS18B20 each are not identical, so it can realize the purpose of a bus to hook up multiple DS18B20. The internal structure of [2] as shown in figure DS18B20 temperature conversion DS18B20 the temperature sensor for temperature measurement can be pleted, in 12 transformation, for example: using 16bit binary plement sign extension reading form, expressed in the form of ℃ / LSB, which S for the sign bit. See table 1: The binary plement form temperature in table 1 Bit 7 Bit 6 Bit 543210 Ls byte Bit Bit Bit 13 14 151112 Bit 10 Bit 98 Ms byte S S S S S This is 12 conversion after the 12 data stored in the 18 b20 two 8 bits of RAM, the front five binary is the sign bit, if measured temperature greater than 0, the five to 0, so long as will detect the numerical x can get to the actual temperature。 And write zero sequence way: after the MCU to bring down the bus, just keep a low level during the entire sequence can be (at least 60 us). Write sequence 15 to 60 us after the initial period, the sampling bus level single bus device. If the sampling for high level during this period, the logic 1 is written to the device。 If sen