schedulingforreducedcpuenergy-在線瀏覽
2024-08-27 17:01本頁面
【正文】 tic Energy Savings ? As the clock speed is reduced by n, energy per cycle can be reduced n2 ? Three methods to achieve this ? Voltage reduction ? Reversible logic ? Adiabatic switching An Energy Metric for CPUs cont’d ? Voltage Reduction ? E/clock is directly proportional to V2 ? Lowervoltage, slowerclock chip。 50ms idle ? Method 2 ? 100ms half speed at half voltage ? Energy consumption: 4:1 Approach of This Paper ? Energy Saving Technique ? The fine grain control of CPU clock speed ? Running slower and at reduced voltage ? Evaluation ? Using tracedriven simulation ? Goal ? To evaluate the energy savings ? To measure the effect of running too slow Trace Data ? From the UNIX scheduler ? Workloads ? S/W dev., documentation, , simulation, ... ? Typing, scrolling ? Time stamp: microsecond ? Sleep events: wait on hard, soft events ? Hard events: disk wait, page fault ? Soft events: keystroke, awaiting work packets ? Soft idle can be eliminated by rescheduling ? Hard idle is mandated by a wait on a device Assumptions ? Simulation ? Soft events belongs to idle periods ? No reordering of trace data events ? Using no energy when idle ? Taking no time to switch speeds ? No consideration of 30 second period of greater than 90% idleness ? Lower bound to practical speed: ? =
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