【正文】 risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the ponent and at the system level. Intel Platform Engineering department developed an objectoriented multithreaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental ponents, and how to use AT89C51. IntroductionThe 8bit AT89C51 CHMOS microcontrollers are designed to handle highspeed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for highspeed event control systems. Commercial applications include modems, motorcontrol systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in enginecontrol systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced onchip peripheral functions set, such as automotive powertrain control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable costeffective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or antilock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of ponents is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the ponent. To mitigate these problems, it is essential that prehensive testing of the controllers be carried out at both the ponent level and system level under worst case environmental and voltage conditions. This plete and thorough validation necessitates not only a welldefined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various microcontrollers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device. The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16bittimer/counters, a five vector twolevel interrupt architecture, a full duple serial port, onchip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys tem to continue functioning. The Powerdown Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Figure 121Block Diagram13Pin DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1：Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the loworder address bytes during Flash programming and verification.Port 2：Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVXDPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder ad