【正文】 temperature testing system design preface With the development of society and the technological progress, people pay more and more attention to the importance of temperature detection and display. Temperature detection and status display technology and equipment has been widely applied in industries, products on the market emerge in endlessly. Temperature testing and also gradually adopt the automatic control technology to realize the monitor. This topic is a temperature testing and status of the monitoring system. System solutions This system USES the monolithic integrated circuit AT89C51 as this system. The whole system, the hardware circuit including power supply circuit, sensor, the temperature display circuit circuit, upper alarm circuit . The alarming circuit can be measured in upper temperature range, screaming voice alarm. The basic principle for the temperature control DSl8B20: when the temperature signal acquisition to after temperature signal sent to handle, AT89C51 temperature to LCD screen, SCM according to initialize the upper temperature setting, namely, if the judgement of temperature than the highest temperature cooling fan is started, If the temperature is less than the lowest temperature setting on alarm device. The system hardware design （ 1） AT89C51 SCM are introduced The AT89C51 is a lowpower, highperformance CMOS 8bit microputer with 4K bytes of Flash programmable and erasable read only memory (PEROM) and 128 bytes of data randomaccess memory(RAM). The device is manufactured using ATMEL Co.’s highdensity nonvolatile memory technology and is patible with the industrystandard MCS51 instruction set and pinout. The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with Flash on a monolithic chip, the ATMEL Co.’s AT89C51 is a powerful microputer which provides a highlyflexible and costeffective solution to many embedded control applications. Features: 4K bytes of insystem reprogrammable Flash memory 中原工學院信息商務學院外文 翻譯 10 Fully static operation: 0 Hz to 24 MHz 1288bit internal RAM Two 16bit Timer/Counters Programmable serial channel VCC: Supply voltage Port 0: Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification. Port 2: Port 2 is an 8bit bidirectional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory which uses 16bit addresses (MOVX DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8bit addresses (MOVX RI). Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. PSEN ： Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. XTAL1： Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Ready/ BUSY : The progress of byte programming can also be monitored by the RDY/BSY output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY. Oscillator Characteristics： XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode： In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write t