【正文】 core and/or peripheral design flaw. In addition, field replacements of ponents is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the ponent. To mitigate these problems, it is essential that prehensive testing of the controllers be carried out at both the ponent level and system level under worst case environmental and voltage conditions. This plete and thorough validation necessitates not only a welldefined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various microcontrollers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device. The AT89C51 provides the following standard features 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16bittimer/counters, a five vector twolevel interrupt architecture, a full duple serial port, onchip oscillator 安徽理工大學(xué)畢業(yè)設(shè)計(jì)外文文獻(xiàn)翻譯 3 and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys tem to continue functioning. The Powerdown Mode saves the RAM contents but freezes the oscil– lator disabling all other chip functions until the next hardware reset. Description VCC Supply voltage. GND Ground. Port 0： Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification. Port 1： Port 1 is an 8bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can sink/so urce four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the loworder address bytes during Flash programming and verification. Port 2： Port 2 is an 8bit bidirectional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVXDPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder 安徽理工大學(xué)畢業(yè)設(shè)計(jì)外文文獻(xiàn)翻譯 4 address bits and some control signals durin Flash programming and verification. Port 3： Port 3 is an 8bit bidirectional I/O port with internal pull ups. The Port 3 output buffers can sink/sou rce four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: RST： Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG： Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN： Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP： External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin alsreceives the 12volt programming enable voltage (VPP) during Flash