【正文】 單的三步過程在全部過程完成之后總線主機(jī)便知道一個(gè)器件中 ROM的內(nèi)容器件中其余的數(shù)以及他們的 ROM編碼可以游另外一個(gè)過程來識(shí)別 以下 ROM 搜索過程的例子假設(shè)四個(gè)不同的器件連接到同一條單線總 線上四個(gè)器件的 ROM 數(shù)據(jù)如下所示 ROM1 00110101 ROM2 10101010 ROM3 11110101 ROM4 00010001 搜索過程如下 1 總線主機(jī)通過發(fā)出復(fù)位脈沖開始初始化序列從屬器件通過發(fā)出同時(shí)的存在脈沖作出響應(yīng) 2 然后總線主機(jī)在單線總線上發(fā)出搜索人 ROM 命令 3總線主機(jī)從單線過程中讀一位每一器件通過把他們各自 ROM數(shù)據(jù)的第一位的值放到單線總線上來作出響應(yīng) ROM1和 ROM4將把一個(gè) 0放在單線總線上即把它拉至低電平 ROM2 和 3 通過使總線停留在高電平而把 1 放在單 線總線上結(jié)果是線上所有器件的邏輯與因此總線主機(jī)接收到一個(gè) 0總線主機(jī)讀另一位因此搜索 ROM數(shù)據(jù)命令正在執(zhí)行所以單線總線上所有器件通過把各自 ROM 數(shù)據(jù)第一位的補(bǔ)碼放到單線總線上來對(duì)這第二個(gè)讀作出響應(yīng) ROM1和 ROM2把 1放在單總線上使之處于高電平 ROM2 和 ROM3 把 0 放在單線上因此他將被拉至低電平對(duì)于第一個(gè) ROM數(shù)據(jù)位的補(bǔ)碼總線主機(jī)觀察到得仍是一個(gè) 0 總線主機(jī)便可決定單線總線上有一些第一位為 0 的器件和一些第一位為 1 的器件 4 總線主機(jī)寫一個(gè) 0 在這次搜索過程的其余部分將不選擇 ROM2和 ROM3 僅留下連接到單線總線的 ROM1 和 ROM4 5總線主機(jī)再執(zhí)行兩次讀并在一個(gè) 1位之后接收到一個(gè) 0位這表示所有還連接在總線上的器件的第二個(gè) ROM 數(shù)據(jù)位為 0 6 總線主機(jī)接著寫一個(gè) 0 使 ROM1 和 ROM4 二者保持連接 7總線主機(jī)執(zhí)行兩次連讀并接收到兩次 0數(shù)據(jù)位這表示連接著的器件 ROM數(shù)據(jù)的第三位都是 1 數(shù)據(jù)位和 0 數(shù)據(jù)位 8總線主機(jī)寫一個(gè)數(shù)據(jù)位這將不選擇 ROM1而把 ROM4作為唯一仍連接著的器件加以保留 9 總線主機(jī)讀 ROM4 的 ROM 數(shù)據(jù)位的剩余部分而且訪問需要的部件這就完成了第一個(gè)過程并且唯一的識(shí)別單線總線上的部件 10 總線主機(jī)通過重復(fù)步驟 1 至 7 開始一個(gè)新的 ROM 搜索序列 11 總線主機(jī)寫一個(gè) 1 這將不與 ROM4 發(fā)生聯(lián)系而唯一的與 ROM1 仍保持著聯(lián)系 12總線主機(jī)對(duì)于 ROM1讀出 ROM位的剩余部分而且如果需要的話與內(nèi)部邏輯通信這就完成了第二個(gè) ROM 搜索過程在其中 ROM 中的另一個(gè)被找到 13 總線主機(jī)通過重復(fù)步驟 1 至 3 開始一次新的 ROM 搜索 注意下述內(nèi)容 在第一次 ROM 搜索過程中總線主機(jī)知道一個(gè)單線器件的唯一的 ID 號(hào)取得部件唯一 ROM 編碼的時(shí)間為 960us 8364 us 1316ms 因此總線主機(jī)每秒鐘能夠識(shí)別 75 個(gè)不同的單線器件 The Description of AT89S51 1 General Description The AT89S51 is a lowpower highperformance CMOS 8bit microcontroller with 4K bytes of InSystem Programmable Flash memory The device is manufactured using Atmels highdensity nonvolatile memory technology and is patible with the industrystandard 80C51 instruction set and pinout The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer By bining a versatile 8bit CPU with InSystem Programmable Flash on a monolithic chip the Atmel AT89S51 is a powerful microcontroller which provides a highlyflexible and costeffective solution to many embedded control applications The AT89S51 provides the following standard features 4K bytes of Flash 128 bytes of RAM 32 IO lines Watchdog timer two data pointers two 16bit timercounters a fivevector twolevel interrupt architecture a full duplex serial port onchip oscillator and clock circuitry In addition the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timercounters serial port and interrupt system to continue functioning The Powerdown mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next external interrupt or hardware reset 2 Ports Port 0 is an 8bit open drain bidirectional IO port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as highimpedance inputs Port 0 can also be configured to be the multiplexed loworder addressdata bus during accesses to external program and data memory In this mode P0 has internal pullups Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification External pullups are required during program verification Port 1 is an 8bit bidirectional IO port with internal pullups The Port 1 output buffers can sinksource four TTL inputs When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current IIL because of the internal pullups Port 1 also receives the loworder address bytes during Flash programming and verification Port Pin Alternate Functions P15 MOSI used for InSystem Programming P16 MOSO used for InSystem Programming P17 SCK used for InSystem Programming Port 2 is an 8bit bidirectional IO port with internal pullups The Port 2 output buffers can sinksource four TTL inputs When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pullupsPort 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses MOVX DPTR In this application Port 2 uses strong internal pullups when emitting 1s During accesses to external data memory that use 8bit addresses MOVX RI Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the highorder address bits and some control signals during Flash programming and verification Port 3 is an 8bit bidirectional IO port with internal pullups The Port 3 output buffers can sinksource four TTL inputs When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current IIL because of the pullups Port 3 receives some control signals for Flash programming and verification Port 3 also serves the functions of various special features of the AT89S51 as shown in the following table Port Pin Alternate Functions P30 RXD serial input port P31 TXD serial output port P32 INT0 external interrupt 0 P33 INT1 external interrupt 1 P34 T0 timer 0 external input P35 T1 timer 1 external input P36 WR external data memory write strobe P37 RD external data memory read strobe 3 Memory Organization MCS51 devices have a separate address space for Program and Data Memory Up to 64K bytes each of external Program and Data Memory can be addressed 31 Program Memory If the EA pin is connected to GND all program fetches are directed to external memory On the AT89S51 if EA is connected to VCC program fetches to addresses 0000H