有關(guān)單片機(jī)at89c51中英文翻譯-展示頁(yè)
2024-09-07 04:21本頁(yè)面
【正文】 Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Data polling may begin any time after a write cycle has been initiated.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper bination of control signals and by holding ALE/ low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be reprogrammed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows:(030H) = 1EH indicates manufactured by ATMEL(031H) = 51H indicates AT89C51 singlechip(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming Interface:Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate bination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to pletion.Note: The Information In English Come FromFifth, May 2004, zhonghanmin ，the National Institute of Imformation and Computer TechnologyAT89C51AT89C51是美國(guó)ATMEL公司生產(chǎn)的低電壓，高性能COMS8位單片機(jī)，片內(nèi)含4Kbytes的可反復(fù)擦寫的只讀程序存儲(chǔ)器（PEROM）和128bytes的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（RAM），器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS51指令系統(tǒng)，片內(nèi)置通用8位中央處理器（CPU）和Flash存儲(chǔ)單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)合，可靈活應(yīng)用于各種控制領(lǐng)域。XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.：Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory.RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.Port 2: Port 2 is an 8bit bidirectional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory which uses 16bit addresses (MOVX DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8bit addresses (MOVX RI). Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the highorder address bits and some control signals during Flash programming and verification.Port 0: Port 0 is an 8bit opendrain bidirectional I/O port. As an
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