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【正文】 license from Intel. Design Melds RISC and Microcontroller Ideas The CPU resembles most RISC processors but has smaller registers. It was originally developed by a pair of researchers in Trondheim,Norway, before their consultancy was acquired by Atmel in 1995. Core CPU development still takes place in Norway, while memory and peripheral development is centered in Atmel’s San Jose (Calif.) facility. The core features 32 identical 8bit registers, as Figure 1 shows. Any register can hold addresses or data. Since 8bit address pointers are fairly worthless even in an 8bit device, the last six registers can be used in pairs, as address pointers. Dubbed X, Y, and Z, these three metaregisters can be used for any load or store operation. The pointers can be post incremented or predecremented at the programmer’s option. Finally, a 6bit displacement can be added to the contents of the pointer, a useful option for addressing array elements. This mode is not available for the X pointer。 that op code is reserved for the LDI (load immediate constant) instruction. Figure 1. Unlike other 8bit controllers, AVR has a set of 32 8bit registers. The last six registers can be paired to form three address pointers. As with many lowend microcontrollers, the register file is mapped into the address space, and vice versa. The first 32 bytes of memory, 0x00–0x1F, correspond to registers R0–R31. The chip’s status register—which contains the overflow, carry, sign, and other flags—as well as other ―internal‖ registers are also memory mapped. This allows any register to be manipulated using standard memory references instead of special controlregister instructions. For all intents and purposes, the CPU has no pipeline. It retrieves both source operands, executes the instruction, and stores the result in a single clock cycle. Branch latency is one clock for taken branches. All operations are registertoregister。 although data pointers can be 16 bits, the PC (program counter) is only 12 bits wide, for 8K of code space. Instruction Set As Regular As Possible The pact instruction set necessarily forces some promises, the first of which affects immediate values (literals). Very few instructions accept immediate values, and those that do (ADIW, SUBI, ORI, etc.) work only on the upper half (R16–R31) of the register set, as Table 1 shows. Even after shaving a bit from the operandspecified field, these instructions sometimes have room for only 6bit immediate values. Table 1. Atmel’s AVR 8bit RISC instruction set follows a strict load/store model, with a few simple indirect addressing modes, including post increment and preferment. The architecture also includes a number of individual bitmanipulation instructions. The ADIW and SBIW instructions (add/subtract immediate from word) are even more restrictive, operating on only the last eight registers, R24–R31. These instructions are meant primarily to add small offsets (0–63 bytes) to the X, Y, and Z pointers. There is a wealth of conditional branch instructions: namely, two for each of the eight flags in the status register. With little 7bit offsets, these instructions can def
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