單片機(jī)基礎(chǔ)畢業(yè)設(shè)計(jì)外文翻譯-單片機(jī)-展示頁(yè)
2025-01-31 07:54本頁(yè)面
【正文】 Flash programming and verification. Port 3 Port 3 is an 8bit bidirectional I/O port with internal Port 3 output buffers can sink/source four TTL 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program the AT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to , however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming, for parts that require 12volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration Powerdown Mode In the powerdown mode, the oscillator is stopped, and the instruction that invokes powerdown is the last instruction executed. The onchip RAM and
教學(xué)課件相關(guān)推薦
鄂ICP備17016276號(hào)-1