[電腦基礎(chǔ)知識(shí)]hwswcodesign-文庫(kù)吧資料
2025-01-25 15:24本頁(yè)面
【正文】 合 : list ? 值得考慮的問題 : reuse of hardware (Core) Software synthesis ? 估算困難 ? 對(duì)于嵌入式系統(tǒng)來(lái)說(shuō)，會(huì)有更多的限制 : ? no swapping devices ? no stacks ? only polling and static variables ? 簡(jiǎn)單的算法 ? Translating FSMs to programs especially simple ? 協(xié)同任務(wù)描述 ? Problem: How do we find a linear execution order that satisfies the timing constraints? ? Use scheduling theory. Interface synthesis ? processor and ASIC接口 ? synthesis of software ? synthesis of “glue logic” ? 總線接口的自動(dòng)生成 ? PCI, VME, …… ? sensors and actuators接口 ? 挑戰(zhàn) : SoC with many cores! All Interfaces for HW/SW CoDesign Company Name Member Product Connections Interface Cadence Products CoWare N2C Integrator HDLI NcSim Mentor Graphics Detail in web station Synopsys Detail in web station 4. HWSW cosimulation? ? 基本定義 : 用軟件控制硬件的仿真 ? 目標(biāo) : 把運(yùn)行在一個(gè)可編程的處理器硬件上的虛弱的可編程（ or 固定）硬件子系統(tǒng)和仿真軟件聯(lián)結(jié) Cosimulation Requirements ? 速度 在不同結(jié)構(gòu)下能夠快速測(cè)試輸入的不同激勵(lì) ? 交互式 快速改變結(jié)構(gòu)參數(shù) 容易分析結(jié)果和調(diào)試 (graphical interface) ? 正確性 hardly patible with speed and interactivity 5. 現(xiàn)有工具： 大學(xué)： 商業(yè)： POLIS: . Arexys: Berkeley Coware: C/C++ PTOLEMY: . LavalLogic: Java to Berkeley Verilog VULCAN: Stanford U. Cynlib: C++ to Verilog (Hardware C) Art, Algorithm to CHINOOK:U. of RT: C++ to RTL Washington (VHDL) SUPERLOG: System COSYMA: U. of level description Braunschweig (C*) Available tools ? Cadance (basic and VCC) ? INRIA CADP ? Xtensa from Tensilica ? VxWorks, Montavista RTOS ? IBM PowerPC development platform ? Xilinx’s FPGA Express ? Ptolemy, Polis environment ? Code Composer
教學(xué)課件相關(guān)推薦
鄂ICP備17016276號(hào)-1