【正文】 age on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the remended circuit), the parator delay can be pensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second order breaks will cause significant nonlinearities in the first few counts of the instrument. See Application Note AN017. The minimum clock frequency is established by leakage on the autozero and reference caps. With most devices, measurement cycles as long as 10s give no measurable leakage error. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz, 40kHz, 33 31 kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 250kHz, 16632 kHz, 125kHz, 100kHz, etc. would be suitable. Note that 100kHz ( readings/sec) will reject both 50Hz and 60Hz. The clock used should be free from significant phase or frequency jitter. Several suitable lowcost oscillators are shown in the Typical Applications section. The multiplexed output means that if the display takes significant current from he logic supply, the clock should have good PSRR. ZeroCrossing FlipFlop The flipflop interrogates the data once every clock pulse after the transients of the previous clock pulse and halfclock pulse have died down. False zerocrossings caused by clock pulses are not recognized. Of course, the flipflop delays the true zerocrossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of phase 3. This onecount delay pensates for the delay of the zerocrossing flipflop, and allows the correct number to be latched into the display. Similarly, a onecount delay at the beginning of phase 1 gives an overload display of 0000 instead of 0001. No delay occurs during phase 2, so that true ratiometric readings result. Evaluating The Error Sources Errors from the ”ideal” cycle are caused by: 1. Capacitor droop due to leakage. 2. Capacitor voltage change due to charge “suckout” (the reverse of charge injection) when the switches turn off. 3. Nonlinearity of buffer and integrator. 4. Highfrequency limitations of buffer, integrator, and parator. 5. Integrating capacitor nonlinearity (dielectric absorption). 6. Charge lost by RFFC in charging STRAYC 7. Charge lost by AZC and INTC to charge STRAYC Each error is analyzed for its error contribution to the converter in application notes listed on the back page, specifically Application Note AN017 and Application Note AN032. Noise The peaktopeak noise around zero is approximately 15181。V input, 2 to 3 with a 250181。s period) half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 181。A, and the exact value of integrating resistor may be chosen by: Integrating Capacitor The product of integrating resistor and capacitor should be selected to give the maximum voltage swing which ensures that the tolerance builtup will not saturate the integrator swing (approx. from either supply). For +5V supplies and analog COMMON tied to supply ground, a + to +4V full scale integrator swing is fine, and F is nominal. In general, the value of CINT is given by: A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale , and any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. AutoZero and Reference Capacitor The physical size of the autozero capacitor has an influence on the noise of the system. A larger capacitor value reduces system noise. A larger physical size increases system noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible . The dielectric absorption of the reference cap and autozero cap are only important at poweron or when the circuit is recovering from an overload. Thus, smaller or cheaper caps can be used here if accurate readings are not required for the first few seconds of recovery. Reference Voltage The analog input required to generate a full scale output is REFIN VV 2? The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is remended that a high quality reference be used where highaccuracy absolute meas