單片機(jī)外文翻譯4-單片機(jī)-文庫吧資料
2025-01-27 07:57本頁面
【正文】 of Flash, 256 bytes of RAM, 32 I/O lines, three 16bit timer/counters， a sixvector twolevel interrupt architecture,a full duplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but feezes the oscillator, disabling all other chip functions until the next hardware reset. 3. Pin Description vcc Supply voltage. GND Ground. Port 0 Port 0 is an 8bit open drain bidrectional I/O port. As an output port, each pin can sink eight TTL mputs. When ls are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to extemal program and data memory. In this mode, P0 has intemal pullups. Port 0 also receives the code bytes during Flash programming and outputs the ∞de bytes during program verification. Extemal pullups are required during Program verification. Port 1 Port 1 is an 8bit bidirectional 1/0 port with intemal pullups. The Port 1 output buffers can sink/source four TTL inputs. When Is are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are extemally being pulled low will source current (IlL) because of the intemal pullups. 1n addition, and can be configured to be the timer/counter 2 extemal count input() and the timer/counter 2 trigger input (), respectively， as shown in the following table. Port 1 also receives the loworder address bytes during Flash programing and verification. Port 2 Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When Is are written to Port
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