【正文】 ss transceiver node addresses of the actual system is set by ourselves (4 bytes). In order to improve the reliability of the system, the protocol is designed as stopwait mode. In data link layer, the send process is roughly as follow. Firstly, the data sources send a connection request to the data targets, and it will transfer data after the data sources respond. Then wait for response from data target after each transmission. If the response is correct, another transmission will start. After all the data transmission is done, the data source will send a request to release channel resources, the transmission is finished when the response from the target is received. The receive process is as follow: the data target will receive data after give a response to the source, and will give a effective or uneffective response, until receive a demolition request. Then, save the data and send a response to end the entire process. data values are serially transferred, pumped into a shift register and are then internally available for parallel processing. Here we already see an important point, that must be considered in the philosophy of SPI bus systems: The length of the shift registers is not fixed, but can differ from device to device. Normally the shift registers are 8Bit or integral multiples of it. Of course there also shift registers with an odd 9 number of bits. For example two cascaded 9Bit EEPROMs can store 18Bit data. If a SPI device is not selected, its data output goes into a highimpedance state, so that it does not interfere with the currently activated devices. When cascading several SPI devices, they are treated as one slave and therefore connected to the same chip select [5]. In figure 4 the cascaded devices are evidently looked at as one larger device and receive therefore the same chip select. The data output of the preceding device is tied to the data Ⅴ .SYSTEM TESTING Because munication between any two nodes may be tested through point to point, in this system Testing Process, munication model between node A and node B is a good example for testing schematic diagram, just like figure 10. Closedloop testing circuit is put up through PC with double serial ports and two RS232 ports and munication node A and B. On one terminal, data was sent through serial port testing auxiliary tool “serial port assistant ”, on the other terminal, returning data is monitored. Data is sent through PC’s serial port A, RS232 port, then data buffer and finally wireless transceiver module successively. However, the process of data receiving was SPI serial, data buffer, then RS232 port, finally PC. In t In this paper, a lowpowered and highperformance wireless data munication system were designed with the principle of transceiver nRF905 and 51 series of singlechip puter as the core hardware. An available solution to the wireless data munications was put forward, and this solution was good at stronger realtime response, higher reliability requirement and smaller data amount, which is widely applied various fields such as data munications, environmental monitoring and security Guard System. We believe that integrated and intelligent Communication Protocol are realized after software design is refined and improved testing process, digital oscilloscope was also used to monitor the data transfer of munication node A , node B , RS232 port and SPI port. In the following section, information from MOSI/SCK and MISO/SCK was analyzed to verify the system’s Correctness. As a wavef