【正文】 Large advances and market opportunities. Measurement and Control, 1998, (3): 8085. [23] 荀殿棟 , 程宗匯 . 實用數(shù)字電路設計 . 北京 : 電子工業(yè)出版社 , 1994. [24] 趙維琴 , 李圓圓 . 基于 MCS51 單片機的自動報警系統(tǒng) . 儀表技術 , 2021, (2): 1920. [25] Yuan Weiqi, Zheng chuanqin. Paper Cuweney Recognition System Based on DSP. Internation Electronic Elements, 2021. [26] 陳粵初 . 單片機應用系統(tǒng)設計與實踐 . 北京 : 北京航空航天大學出版社 , 1992. 附錄 A 35 附錄 A 圖 1 紅外監(jiān)測電路 Top Layer 圖 2 紅外監(jiān)測電路 Bottom Layer 圖 3 紅外監(jiān)測電路 3D 效果圖 圖 4 穩(wěn)壓電源電路 Top Layer 圖 5 穩(wěn)壓電源電路 Bottom Layer 基于單片機的紅外監(jiān)測與報警設計與實現(xiàn) 36 圖 6 穩(wěn)壓電源電路 3D 效果圖 圖 7 單片機電路 Top Layer 附錄 A 37 圖 8 單片機電路 Bottom Layer 圖 9 單片機電路 3D 效果圖 基于單片機的紅外監(jiān)測與報警設計與實現(xiàn) 38 附錄 B ORG 0000H LJMP MAIN ORG 0003H LJMP EXINT ORG 0200H MAIN: MOV R1,03H // 數(shù)據(jù)初始化 MOV TMOD,10H MOV TH1,0BH MOV TL1,0DCH CLR ET1 CLR TR1 CLR IT0 SETB EX0 SETB EA HERE: SJMP $ ORG 0400H EXINT: // 中斷程序 JNB ,LEXT1 JNB ,LEXT2 JNB ,LEXT3 JNB ,LEXT4 DONE: RETI LEXT1: LJMP EXT1 LEXT2: LJMP EXT2 LEXT3: LJMP EXT3 LEXT4: LJMP EXT4 ORG 1000H EXT1:MOV P0,06H // 紅外監(jiān)測 1 CLR EX2: MOV R2,0FAH CLR EX3: CLR LCALL DELAY1 SETB LCALL DELAY1 DJNZ R2,EX3 EX4: SETB SETB 附錄 B 39 MOV R0,28H SETB TR1 LCALL DELAY DJNZ R1,EX2 MOV R1,03H SETB LJMP DONE EXT2: MOV P0,5BH // 紅外監(jiān)測 2 CLR EX5: MOV R3,02H EX6: MOV R2,7DH CLR EX7: CLR LCALL DELAY1 SETB LCALL DELAY1 DJNZ R2,EX7 SETB SETB LCALL DELAY2 DJNZ R3,EX6 MOV R0,20H SETB TR1 LCALL DELAY DJNZ R1,EX5 MOV R1,03H SETB LJMP DONE EXT3: MOV P0,4FH // 紅外監(jiān)測 3 CLR EX8: MOV R3,03H EX9: MOV R2,4BH CLR EX10: CLR LCALL DELAY1 SETB LCALL DELAY1 DJNZ R2,EX10 SETB SETB 基于單片機的紅外監(jiān)測與報警設計與實現(xiàn) 40 LCALL DELAY2 DJNZ R3,EX9 MOV R0,20H SETB TR1 LCALL DELAY DJNZ R1,EX8 MOV R1,03H SETB LJMP DONE EXT4: MOV P0,66H // 紅外監(jiān)測 4 CLR EX11: MOV R3,04H EX12: MOV R2,32H CLR EX13: CLR LCALL DELAY1 SETB LCALL DELAY1 DJNZ R2,EX13 SETB SETB LCALL DELAY2 DJNZ R3,EX12 MOV R0,20H SETB TR1 LCALL DELAY DJNZ R1,EX11 MOV R1,03H SETB LJMP DONE ORG 2021H DELAY: JB TF1,LOOP1 // 延時程序 AJMP DELAY LOOP1: MOV TH1,0BH MOV TL1,0DCH CLR TF1 DJNZ R0,DELAY CLR TR1 RET DELAY1: MOV R7,14H DY1: MOV R6,7DH 附錄 B 41 DY2: DJNZ R6,DY2 DJNZ R7,DY1 RET DELAY2: MOV R7,05H DY3: MOV R6,0C8H DY4: MOV R5,7DH DY5: DJNZ R5,DY5 DJNZ R6,DY4 DJNZ R7,DY3 RET END 基于單片機的紅外監(jiān)測與報警設計與實現(xiàn) 42 附錄 C The General Situation of AT89C51 Chapter 1 The application of AT89C51 Abstract: Microcontrollers are used in a multitude of mercial applications such as modems, motorcontrol systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such highspeed eventbased applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the ponent and at the system level. The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16bittimer/counters, a five vector twolevel interrupt architecture, a full duple serial port, onchip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Powerdown Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC: Supply voltage. GND: Ground. Port 0: Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1: Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the loworder address bytes during Flash programming and verification. Port 2: Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits t