【正文】 F Thermometer resolution is programmable from 9 to 12 bits Converts 12bit temperature to digital word in 750 ms Userdefinable nonvolatile temperature alarm settings Alarm search mand identifies and addresses devices whose temperature is outside of programmed limits temperature alarm condition Applications include thermostatic controls industrial systems consumer productsthermometers or any thermally sensitivesystem PIN ASSIGNMENT PIN DESCRIPTION GND Ground DQ Data InOut VDD Power Supply Voltage NC No Connect DETAILED PIN DESCRIPTION OVERVIEW The block diagram of Figure 1 shows the major ponents of the DS18B20 The DS18B20 has four main data ponents 1 64bit lasered ROM 2 temperature sensor 3 nonvolatile temperature alarm triggers TH and TL The device derives its power from the 1Wire munication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1Wire line until it returns high to replenish the parasite capacitor supply As an alternative the DS18B20 may also be powered from an external 3 volt 55 volt supply DS18B20 BLOCK DIAGRAM Figure 1 Communication to the DS18B20 is via a 1Wire port With the 1Wire port the memory and control functions will not be available before the ROM function protocol has been established The master must first provide one of five ROM function mands 1 Read ROM 2 Match ROM 3 Search ROM 4 Skip ROM or 5 Alarm Search These mands operate on the 64bit lasered ROM portion of each device and can single out a specific device if many are present on the 1Wire line as well as indicate to the bus master how many and what types of devices are present After a ROM function sequence has been successfully executed the memory and control functions are accessible and the master may then provide any one of the six memory and control function mands One control function mand instructs the DS18B20 to perform a temperature measurement The result of this measurement will be placed in the DS18B20s scratchpad memory and may be read by issuing a memory function mand which reads the contents of the scratchpad memory The temperature alarm triggers TH and TL consist of 1 byte EEPROM each If the alarm search mand is not applied to the DS18B20 these registers may be used as general purpose user memory The scratchpad also contains a configuration byte to set the desired resolution of the temperature to digital conversion Writing TH TL and the configuration byte is done using a memory function mand Read access to these registers is through the scratchpad All data is read and written least significant bit first 1WIRE BUS SYSTEM The 1Wire bus is a system which has a single bus master and one or more slaves The DS18B20 behaves as a slave The discussion of this bus system is broken down into three topics hardware configuration transaction sequence and 1Wire signaling signal types and timing HARDWARE CONFIGURATION The 1Wire bus has only a single line by definition it is important that each device on the bus be able to drive it at the appropriate time To facilitate this each device attached to the 1Wire bus must have open drain or 3state outputs The 1Wire port of the DS18B20 DQ pin is open drain with an internal circuit equivalent to that shown in Figure 9 A multidrop bus consists of a 1Wire bus with multiple slaves attached The 1Wire bus requires a pullup resistor of approximately 5 k The idle state for the 1Wire bus is high If for any reason a transaction needs to be suspended the bus MUST be left in the idle state if the transaction is to resume Infinite recovery time can occur between bits so long as the 1Wire bus is in the inactive high state during the recovery period If this does not occur and the bus is left low for more than 480 s all ponents on the bus will be reset HARDWARE CONFIGURATION TRANSACTION SEQUENCE The protocol for accessing the DS18B20 via the 1Wire port is as follows _ Initialization _ ROM Function Command _ Memory Function Command _ TransactionData INITIALIZATION All transactions on the 1Wire bus begin with an initialization sequence The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse s transmitted by the slave s The presence pulse lets the bus master know that the DS18B20 is on the bus and is ready to operate For more details see the 1Wire Signaling section ROM FUNCTION COMMANDS Once the bus master has detected a presence it can issue one of the five ROM function mands All ROM function mands are 8 bits long A list of these mands follows refer to flowchart in Figure 5 Read ROM [33h] This mand allows the bus master to read the DS18B20s 8bit family code unique 48bit serial number and 8bit CRC This mand can only be used if there is a single DS18B20 on the bus If more than one slave is present on the bus a data collision will occur when all slaves try to transmit at the same time open drain will produce a wired AND result Match ROM [55h] The match ROM mand followed by a 64bit ROM sequence allows the bus master to address a specific DS18B20 on a multidrop bus Only the DS18B20 that exactly matches the 64bit ROM sequence will respond to the following memory function mand All slaves that do not match the 64bit ROM sequence will wait for a reset pulse This mand can be used with a single or multiple devices on the bus Skip ROM [CCh] This mand can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64bit ROM code If more than one slave is present on the bus and a Read mand is issued following the Skip ROM mand data collision will occur on the bus as multiple slaves transmit simul