【正文】 在這種羊 128b,有 32 個(gè)單位字節(jié)可以出任就業(yè)登記 ,這是與一般不同的微處理器、 8051 切片和就業(yè)登記成立一個(gè)級(jí)別相同的地點(diǎn)安排 . 這是很不相同的記憶監(jiān)控監(jiān) 51 系列之一 計(jì)算機(jī)芯片 ,除了一般電腦的方式處置 . 一般電腦先向空間、存儲(chǔ)器和 RAM,可安排在不同的空間范圍內(nèi)解決這一意愿 ,即存儲(chǔ)器的地址和 RAM,地址分配不同的空間形成 . 同時(shí)來訪的記憶 ,相應(yīng)的存儲(chǔ)器 ,只有一個(gè)地址 ,可以存儲(chǔ) ,也可以撞擊 ,并以同樣的訪問 . 這種記憶結(jié)構(gòu)稱為普林斯頓結(jié)構(gòu) . 8051 記憶分為程序存儲(chǔ) 空間和數(shù)據(jù)存儲(chǔ)空間的物理結(jié)構(gòu) ,有四個(gè)存儲(chǔ)空間 :我們的程序儲(chǔ)存在一個(gè)數(shù)據(jù)存儲(chǔ)空間之外的數(shù)據(jù)存儲(chǔ)和一個(gè)程序存儲(chǔ)空間、外一、結(jié)構(gòu)形式的這種程序裝置和數(shù)據(jù)存儲(chǔ)與形式的數(shù)據(jù)存儲(chǔ) ,稱為哈佛結(jié)構(gòu) . 但用用戶的角度 ,討論 8051 年的記憶空間分為三類 : 1 在時(shí)代安排 Ffffh 座 ,0000h 地點(diǎn)、從容外片 地址用十六 . 二 處理數(shù)據(jù)存儲(chǔ)空間之外 64kb 之一 ,被安排從地址 0000hFfffh64kb 地址 16 ,地點(diǎn)太 . 三 處理數(shù)據(jù)存儲(chǔ)空間 256b 地址 8 使用 . 上述三個(gè)存儲(chǔ)空間地址重疊 ,鑒別設(shè)計(jì) ,象征不同的數(shù)據(jù)傳輸?shù)?語言系統(tǒng) 8051:CPU訪問片 ,以存儲(chǔ)器 ,阻止訪問命令 Ra用途外用一張旅游片。s head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported instantaneous , can also through is it restore to the throne circuit group holding value carry on the experiment to change. 51 系列單片機(jī)的功能和結(jié)構(gòu) 結(jié)構(gòu)和功能的監(jiān)控監(jiān) 51 系列之一 計(jì)算機(jī)芯片監(jiān)控監(jiān) 51 名是一幅一個(gè)電腦晶片 ,英特爾公司生產(chǎn)系列 . 這家公司推出 8 級(jí)一個(gè)計(jì)算機(jī)芯片監(jiān)控監(jiān) 51 系列之后 ,于 1980 年 8 引入一個(gè)計(jì)算機(jī)芯片監(jiān)控監(jiān) ,于 1976 年 48 系列 .。t mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle namely 2 machine cycles the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal RST hand over to Schmitt39。clock, can output W line signal . At the time of programming, it is that the first function is still the second function but needn39。clock, output Q end signal。 When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on needn39。s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, e from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 onechip puters, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of . This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other puters, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is manded. There are ROM procedure memory , can only read and RAM in 8051 slices data memory, can is it can write two to read, they have each independent memory address space, dispose way to be the same with general memory of puter. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS51 series onechip puter and general puter disposes the way in addition. General puter for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: 1 In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice use 16 addresses . 2 The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH with 16 addresses too to the location. 3 Data memory address space of 256B use 8 addresses . Three abovementioned memory space addresses overlap, for distinguishing and designing the order symbol of different data tran