【正文】 31。當(dāng)一條指令訪問7FH以上的內(nèi)部地址單元時(shí)，指令中使用的尋址方式是不同的，也即尋址方式?jīng)Q定是訪問高128字節(jié)RAM還是訪問特殊寄存器。l 中斷寄存器：AT89C52有6個(gè)中斷源，2個(gè)中斷優(yōu)先級，IE寄存器控制各中斷位，IP寄存器中6個(gè)中斷源的每一個(gè)可定為2個(gè)優(yōu)先級。對沒有定義的單元讀寫是無效的，讀出的數(shù)值將不確定，而寫入的數(shù)據(jù)也將丟失。FLASH存儲器編程時(shí)間，該引腳加上+12的變成允許電源，當(dāng)然這必須是該器件是使用12編程電壓。需注意的是；如果加密LB1被編程，復(fù)位時(shí)內(nèi)部會鎖存EA端狀態(tài)。l EA/VPP：外部訪問允許。l PSEN：程序存儲允許輸出是外部程序存儲器的讀選通信號，當(dāng)AT89C52由外部程序存儲器取指令時(shí)，每個(gè)機(jī)器周期量詞有效，即輸出兩個(gè)脈沖。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時(shí)間、將跳過一個(gè)ALE脈沖。l ALE/PROG；當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時(shí)ALE輸出脈沖用語鎖存地址的低8位字節(jié)。l RST：復(fù)位輸入。P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能。對P3口寫入“1“時(shí)間，它們被內(nèi)部上拉電阻拉高并可作為輸入斷口。l P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙響I/O口。在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器時(shí)，P2口送出高8位地址數(shù)據(jù)。l P2口：是一個(gè)帶有內(nèi)部上拉電阻的8位雙響I/O口，P2的輸出緩沖可驅(qū)動4個(gè)TTL邏輯門電路。做輸入口。l P1口：是一個(gè)帶內(nèi)部上拉電阻的8位雙響I/O口，P1輸出緩沖級可驅(qū)動4個(gè)TTL邏輯門電路。在訪問外部數(shù)據(jù)存儲器或 程序存儲器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，在訪問激活內(nèi)部上拉電阻。引腳功能說明l VCC：電源電壓l GND：地l P0口：P0口是一組8位漏極開路雙向I/O口，也即地址/數(shù)據(jù)總線服用口?？臻e方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。 Low Power Idle and Power Down ModesDescriptionThe AT89C52 is a lowpower, highperformance CMOS 8bit microputer with 8 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is patible with the industry standard 80C51 and 80C52 instruction set and pinout. The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C52 provides the following standard features: 8 Kbytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16bit timer/counters, a sixvector twolevel interrupt architecture, a full duplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89C52 isDescription (Continued)designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, and can be configured to be the timer/counter 2 external count input () and the timer/counter 2 trigger input (), respectively, as shown in the following table.Port 1 also receives the loworder address bytes during Flashprogramming and program verification.port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some controlsignals during Flash programming and verification.Port 3Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Port 3 also receives some control signals for Flash programming and programming verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address