【正文】 簽名： 月 日教研室意見 教研室主任（簽章）： 月 日評(píng)審小組意見 參加評(píng)審人員（簽字）： 月 日指導(dǎo)教師意見 簽名： 月 日教研室意見 教研室主任（簽章）： 月 日評(píng)審小組意見 參加評(píng)審人員（簽字）：。 consult the listing for additional information. With a 12 MHz processor clock and the resulting one microsecond instruction cycle, an eightbit conversion can be performed in under 300 microseconds. The unknown input voltage must be held constant for the duration of the conversion.Obvious disadvantages to the successive approximation analogtodigital converter presented here are the need for bipolar power supplies and the large number of microcontroller I/O pins required to control the DAC. The +15volt supply could be eliminated by replacing the LF355B op amp with a single supply, 5volt, functional equivalent with outputs that swing railtorail. The number of microcontroller I/O pins required to control the DAC could be reduced somewhat by substituting a seven or six bit DAC. The parallel input DAC could be replaced with a (more expensive) serial input DAC. Alternately, logic could be added to accept serial data from the microcontroller and present parallel data to the DAC.The software for this application may be obtained by downloading from Atmel’s BBS: (408) 4364309. Consult the ment block at the beginning of the source code file for detailed information on features and oper功能特性概述：指導(dǎo)教師意見該生接受“數(shù)顯式脈搏計(jì)的設(shè)計(jì)”課題以來，積極查閱并認(rèn)真學(xué)習(xí)資料，對(duì)設(shè)計(jì)要求有較為清晰地理解，對(duì)系統(tǒng)各部分的組成已有初步的設(shè)計(jì)方案。 and 177。 177。 variations in VCC. The contributions to conversion error made by these sources can be expected to increase error to somewhat more than the value due to ponent tolerances alone.Successive Approximation AnalogtoDigital ConverterThis conversion method offers good resolution and accuracy and a short conversion time at the expense of increased ponent count.Successive approximation (SA) ADCs incorporate a digitaltoanalog converter (DAC), a parator and a successive approximation register (SAR). The SAR controls the conversion by performing a search for the binary code which, when fed to the DAC, will produce an output matching the voltage to be converted. The parator pares the DAC output to the unknown voltage and returns the result to the SAR.The SAR begins the search with the most significant DAC bit, which controls the widest output variation, and moves toward the least significant bit, causing the DAC output to “zero in” on the unknown value. The result of the trial is the binary code corresponding to the unknown value. In aneightbit SA converter, only eight iterations are required to find the correct binary code, resulting in relatively fast conversions.In this application (Figure 5), an AT89CX051 microcontroller with an integral analog parator performs the SAR function in software, reducing the ponent count. The DAC selected for the application is an MC14088, eightbit, current output type chosen for its low cost. Seven and six bit versions are available as the MC14087 and MC14086, respectively. The MC1408 series is guaranteed accurate to within 177。 asymmetries between the charge and discharge portions of the cycle。, as shown below. To calculate the worst case error at VC = , first determine the corresponding t at the nominal values of R and C using Equation 3:t = RnomCnom?ln(1VC/VCC)= RnomCnom?ln()= RnomCnom?ln().Substitute for t in Equation 1 to get minimum VC:VCmin = VCC (1et/(Rmax Cmax))= VCC (1e(Rnom Cnom/Rmax Cmax)ln())= 5 (1eln()/(?))≌ VAgain, for maximum VC:VCmax = VCC (1et/(Rmin Cmin))= VCC (1e(Rnom Cnom/Rmin Cmin)ln())= 5 (1eln()/(?))≌ VThe results show a variation of at , or a worst case error of 177。 這應(yīng)用軟件可能從Atmel的BBS 下載獲得： (408)4364309. 請(qǐng)?jiān)谠创a文件的開始時(shí)參見意見塊以獲得關(guān)于特征和操作的詳細(xì)資料。 并行輸入DAC可被連續(xù)的DAC輸入替換(更昂貴)。 +15伏特電源可能通過一個(gè)帶單獨(dú)的電源的LF355B運(yùn)算放大器代替，單獨(dú)的電壓源為5v，作用和在標(biāo)記擺動(dòng)的輸出等同。 未知輸入電壓在變化時(shí)必須保持不變的量。 這種延遲在軟件里適用； 參考附加信息的目錄。DAC輸出設(shè)定時(shí)間和比較器執(zhí)行SA算法所需的響應(yīng)時(shí)間是可以忽略的。正極電源可選擇+15v，這樣可限制運(yùn)算放大器輸出的抖動(dòng)，達(dá)到比較器輸出限制5v以上。15伏雙極的電源。 LF355B運(yùn)算放大器需要提供177。 1240歐電阻器連接 DAC的腳15 ，2500歐電阻器和運(yùn)算放大器腳3 連接可能相抵消，性能稍微下降。隨著I/V變換器獲得電阻器值的改變，結(jié)果可能變化。由于LF355B運(yùn)算放大器振幅有較低偏移電壓，所以偏移電壓不需要調(diào)整。Ro)= 。 輸出電壓由DAC輸出電流( Io)以i/ V變換器的值得乘積來確定。 在DACscales lref用8比特從0/256到255/256二進(jìn)制編碼，輸出結(jié)果從零到(Io)(Iref 0/256) mA(Iref 255/256)。在LM3362. 5數(shù)據(jù)表里表明的方法使基準(zhǔn)電壓和溫度系數(shù)相平衡。 (Vref)。 當(dāng)被編譯電壓超過未知的電壓時(shí)，比較器的輸出變大，這被軟件檢測。LF355B選做電流電壓變化器。 輸入電流由LM3362. 5精密電壓參考源和一臺(tái)連續(xù)電阻器得到。％，保證了八位的單一性和線性。7和6比特型相對(duì)來說適合于MC1407和MC14086。減少元件數(shù)。得到相關(guān)的快速變換。實(shí)驗(yàn)結(jié)果為未知值對(duì)應(yīng)二進(jìn)制編碼。比較器比較DAC未知電壓和輸出，并返回SAR的結(jié)果。并縮短了轉(zhuǎn)換時(shí)間。這些因素造成的變換誤差比單獨(dú)的元件誤差值大。伏特計(jì)元件中使用的電容器是聚苯乙烯薄膜，雖然準(zhǔn)確性不好，但因隔絕了吸收和其他影響而減小了誤差。最差的變換誤差可以通過用較小公差元件來進(jìn)一步減小。首先用方程3確定與r和c一般值對(duì)應(yīng)的t。例子：，伏特計(jì)原件的精度是+/1（）但即使使用精密元件，通過RC模擬－數(shù)字變換方法無法到達(dá)這個(gè)精度。但用來確定表數(shù)。電壓和時(shí)間表現(xiàn)非線性關(guān)系。但是臨近采樣的電壓隨著N的遞增而下降。它可以在每次半周期最后采樣前實(shí)現(xiàn)比一般中間值更快的周期。它變化軌跡決定了表數(shù)的排列。方程4變成：V=5*eN(.0093633)電容器充放電周期電壓計(jì)算略表如下。放電半周期采樣對(duì)應(yīng)電壓通過在方程4中用N代替t計(jì)算。對(duì)充電半周期，通過求解方程一得到電容器開始充電起消耗時(shí)間，來求得每次采樣的電壓。對(duì)每半個(gè)周期，平臺(tái)第N個(gè)值對(duì)應(yīng)t＝（N－1)時(shí)的電壓。查表包含軟件一個(gè)專門值。從方程 3 半周期最小采樣數(shù)為：為了提高準(zhǔn)確性，在周期充電部分電壓計(jì)算從0到VCC/2，而放電部分從VCC到1/2VCC。如果電容電壓上升緩慢，而電容電阻值很大，時(shí)間常數(shù)用最大值計(jì)算。解方程1得到時(shí)間：。波形的充電部分，漸近線在VCC。電容器充放電所需時(shí)間越多，在計(jì)算周期所需的采樣量越多，查找表個(gè)數(shù)越多。時(shí)間恒量（RC）決