【正文】 end one。 end if。 else t=t。139。 thent=0000。) thenif t=1110 and enable=39。event and clk=39。 thent=0000。 process(clk,reset) begin if reset=39。end if。else tc=39。 architecture one of count15 is begin process (t) begin if t=1110 then tc=39。 tc:out bit)。 entity count15 is port( clk, enable, reset:in bit。 end t_pkg。 tc:out bit)。 in this reference, mean that this counter is likely to be used either multiple times in a particular design or across multiple designs. Both are cases where hierarchical design simplifies things.) This counter is a simple fourbit counter, but it must output a terminal count indication (tc) and roll over to zero when it reaches 1110 rather than 1111.A design file that would acplish this is shown in program A. (The reader should understand the contents of the entityarchitecture pair. they will not be discussed further.)Program A: Counter with Terminal Count and Rollover Selectionpackage t_pkg is ponent count15 port( clk, enable, reset:in bit。t implement them.Library A library is a logical storage facility for design a ponent can be instantiated in a higherlevel design unit, its package must be piled into a library that is visible to that design unit, usually the current work library.A library is simply where units are units can be packages or analysed designs (effectively designs that have been piled).Libraries are just a way of grouping related units IEEE library includes all the packages related to the IEEE default working library, into which all analysed design units are stored is called generally map to specified directories in the operating system, with standard subdirectories and files beneath it, representing the library units.Simple ExampleConsider the following example. A designer discovers that for a specific type of circuit design he monly needs an unusual type of counter. (!176。The names of ports in a ponent need not match an entity, can be used for relabelling.Components are instantiated like entities but without the entity keyword.Package A package is a collection of VHDL declarations that can be used by other VHDL descriptions. For the purpose of creating hierarchical designs, a package consists of one or more ponents. However, a package may also include other types of declarations.In large collaborative projects, there is often a need to work off some mon definitions..A package allows us to group a set of related declaration statements for use in many designs. package package_name isdeclaration statementsend package package_name。port_name2 : in | out type)。參考文獻(xiàn)[1] 羅朝霞，高書莉．CPLD/FPGA設(shè)計(jì)及應(yīng)用．北京人民郵電出版社，2007[2] 盧毅，賴杰．VHDL與數(shù)字電路設(shè)計(jì)．北京科學(xué)出版社，2001[3] 曹志剛, 錢亞生．現(xiàn)代通信原理．北京清華大學(xué)出版社，1992[4] 劉皖，何道君，譚明．FPGA設(shè)計(jì)與應(yīng)用．北京清華大學(xué)出版社，2006[5] Stephen Brown，Zvonko Vranesic．?dāng)?shù)字邏輯基礎(chǔ)與VHDL設(shè)計(jì)．北京清華大學(xué)出版社，2011[6] 潘松．VHDL實(shí)用教程．西安電子科技大學(xué)出版社，2000[7] 徐向民．?dāng)?shù)字系統(tǒng)設(shè)計(jì)及VHDL實(shí)踐．北京機(jī)械工業(yè)出版社，2009[8] 褚振勇，翁木云．FPGA設(shè)計(jì)及應(yīng)用．西安電子科技大學(xué)出版社，2002[9] 侯伯亨．VHDL硬件描述語言與數(shù)字邏設(shè)計(jì)．西安電子科技大學(xué)出版社，2001[10] 王毅平，張振榮．VHDL編程與仿真．人民郵電出版社，2000[11] 趙曙光．可編程邏輯器件原理、開發(fā)與應(yīng)用．西安電子科技大學(xué)出版社，2001附錄A 英語原文Using Hierarchy in VHDL DesignIntroductionHierarchical design methodology has been monly use for quite some time by system designers and software developers. There are two primary advantages to using this methodology. First, it allows monlyused building blocks to be created separately and saved for later use without having tredesign or reverify them. Second, it allows for more readable design files by keeping the toplevel design file as a simple integration of smaller building blocks, either userdefined or from a vendorsupplied library. In system design, these building blocks normally take the form of schematic symbols instantiated into a schematic drawing, while in software they are functions or procedures that are called from the main program.VHDL includes a set of features specifically designed to make hierarchical design both simple and powerful. This note will first describe these features and then walk through a simpl example of how they might be used. It assumes that the reader is familiar with how to create a VHDL design unit consisting of an entityarchitecture pair.Key ConceptsIn order to construct a hierarchical design in VHDL, the designer must understand the concepts of ponents, packages and libraries.Component A ponent is a VHDL design unit that may be instantiated in other VHDL design units. Before it can be instantiated, it must be declared using the COMPONENT declaration which specifies the name of the ponent and lists its local signal names.Components are simply wrappers for , ponents had to be used to instantiate an entity, though since VHDL 1993, we can use direct entity instantiation as covered ponent declaration looks identical to an entity declaration.ponent entity_name isport(port_name1 : in | out type。同時(shí)，還要感謝在這段時(shí)間幫助我的同學(xué)們，他們認(rèn)真、扎實(shí)的學(xué)習(xí)態(tài)度深深地感染了我。在整個(gè)課題其間導(dǎo)師一直都給予我鼓勵(lì)，在關(guān)鍵部分的設(shè)計(jì)中給予我技術(shù)上的指導(dǎo)并及時(shí)糾正我存在的一些錯(cuò)誤，同時(shí)，也給我很大的自由發(fā)揮空間。雖然我對專業(yè)知識依舊很欠缺，但是導(dǎo)師的指導(dǎo)和督促讓我所學(xué)頗多。致 謝首先要感謝我的指導(dǎo)老師老師。實(shí)現(xiàn)各種運(yùn)算器的方法單一等問題。通過分析仿真結(jié)果，了解系統(tǒng)性能。然后在QuartusⅡ軟件中進(jìn)行仿真，并對仿真結(jié)果進(jìn)行分析、比較，最后得出結(jié)論，所得的仿真結(jié)果都是正確的。通過該畢業(yè)設(shè)計(jì)，完成了以下內(nèi)容。結(jié) 論本次畢業(yè)設(shè)計(jì)的課題是“基于QuartusⅡ的運(yùn)算器的設(shè)計(jì)與實(shí)現(xiàn)”。end process。d=f。 end loop。 else exit。 for i in 15 downto 0 loop if (f=g) then f:=fg。g:=b。d = 15。architecture rt of chufaqi isbegin process(a,b) variable e,f,g:integer range 16 downto 0。 c,d:out integer range 15 downto 0)。use 。use 。 除法器流程圖 除法器的設(shè)計(jì)與實(shí)現(xiàn)除法器的建立過程可以參見半加器的建立過程。 基于Quartus II的除法器運(yùn)算 除法器的原理與流程圖除法器原理本文所做的除法器是由被除數(shù)減去除數(shù)，當(dāng)被除數(shù)減去除數(shù)小于0的時(shí)候就停止進(jìn)行，則之前減的次數(shù)就是此次運(yùn)算的商，最后一次計(jì)算所剩余的數(shù)就是此次運(yùn)算的商。u5:reg16b port map(intclk,rstall,dtbin,dtbout)。u3:andarith port map(qb,a,andsd