【正文】 圖1。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。用戶也可以采用外部時(shí)鐘。10PF，而如果使用陶瓷振蕩器建議選擇40PF177。對外接電容C1，C2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，如圖1所示。XTAL2：震蕩器反相放大器的輸出端。Flash存儲器編程時(shí)，該引腳加上+12V的編程允許電壓Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。需要注意的是：如果加密位LBI被編程，復(fù)位時(shí)內(nèi)部會鎖存EA端狀態(tài)。/Vpp:外部訪問允許。PSEN：程序儲存允許輸出是外部程序存儲器的讀選通信號，當(dāng)AT89C51由外部程序存儲器讀取指令時(shí)，每個(gè)機(jī)器周期兩次PSEN 有效，即輸出兩個(gè)脈沖。這個(gè)位置后只有一條MOVX和MOVC指令A(yù)LE才會被應(yīng)用。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時(shí)將跳過一個(gè)ALE脈沖時(shí)，F(xiàn)lash閃速存儲器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。ALE/：當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時(shí)，ALE輸出脈沖用于鎖存地址的低8位字節(jié)。RST：復(fù)位輸入。對P3口寫如“1”時(shí)，它們被內(nèi)部電阻拉到高電平并可作為輸入端時(shí)，被外部拉低的P3口將用電阻輸出電流。Flash編程或程序校驗(yàn)時(shí)，P2口接收高位地址和其它控制信號。在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器時(shí)，P2口送出高8位地址數(shù)據(jù)。對端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)，可作為輸入口。Flash編程和程序校驗(yàn)時(shí)，P1口接收低8位地址。對端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。P0口在Flash編程時(shí)，P0口接收指令，在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。當(dāng)“1”被寫入P0口時(shí)，每個(gè)管腳都能夠作為高阻抗輸入端。引腳描述：VCC：電源電壓 GND：地P0口：P0口是一組8位漏極開路雙向I/O口，即地址/數(shù)據(jù)總線復(fù)用口。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。AT89C51提供以下的功能標(biāo)準(zhǔn)：4K字節(jié)閃爍存儲器，128字節(jié)隨機(jī)存取數(shù)據(jù)存儲器，32個(gè)I/O口，2個(gè)16位定時(shí)/計(jì)數(shù)器，1個(gè)5向量兩級中斷結(jié)構(gòu)，1個(gè)串行通信口，片內(nèi)震蕩器和時(shí)鐘電路。和128字節(jié)的存取數(shù)據(jù)存儲器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲技術(shù)生產(chǎn)，并且能夠與MCS51系列的單片機(jī)兼容?？删幊檀蠻ART通道2個(gè)16位定時(shí)/計(jì)數(shù)器128 8字節(jié)內(nèi)部RAM全靜態(tài)操作：0Hz24MHz4k字節(jié)可重復(fù)擦寫Flash閃速存儲器 10 pF for Ceramic ResonatorsFigure 2. External Clock Drive ConfigurationIdle Mode:In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power Down Mode:In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock Bits:On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:When lock bit 1 is programmed, the logic level at the pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash:The AT89C51 is normally shipped with the onchip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high voltage (12volt) or a lowvoltage (Vcc) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the highvoltage programming mode is patible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the highvoltage or lowvoltage programming mode enabled. The respective topside marking and device signature codes are listed in the following table.Vpp=12VVpp=5VTopSide MarkAT89C51xxxxyywwAT89C51xxxx5yywwSignature(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HThe AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct bination of control signals.4. Raise /Vpp to 12V for the highvoltage programming mode. 5. Pulse ALE/ once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Polling:The AT89C51 features Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Polling may begin any time after a write cycle has been initiated. Ready/: The progress of byte programming can also be monitored by the RDY/ output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper bination