【正文】 Differential Pairing Copyright 169。 2022 Altera Corporation 110 Pin Planner Features ? Displays I/O Banks, VREF Groups amp。 Drop Pin Assignments ? Set Pin I/O Standards ?Three Sections ? Unassigned Pins List ? Package View ? Assigned Pins List Assignments Menu ? Pin Planner Copyright 169。 2022 Altera Corporation 107 I/O (Pin) Assignments ?Pin Planner ?Assignment Editor ?Import from Spreadsheet in CSV Format ?QSF File ?Timing Closure Floorplan ? Shows Pin Pad Distances ? Shows Relationships with Core ?Scripting Copyright 169。 2022 Altera Corporation 105 Output Pin Load ? Specifies Output Pin Loading in picoFarads (pF) ? Changes Default Loading Value of I/O Standard ? Changes tco of Output Pins ? Allows Designer to Accurately Model Board Conditions ? Must Be Applied to Output or Bidirectional Pins Copyright 169。 Logic Mapping ? Only Applies to Quartus II Integrated Synthesis Copyright 169。 2022 Altera Corporation 102 Example Assignments ?Optimization Technique ?PCI I/O ?Output Pin Load Copyright 169。 2022 Altera Corporation 100 AE Tcl Commands ? Equivalent Tcl Commands Are Displayed as Assignments Are Entered ? Manually Copy to Create Tcl Scripts ? Export Command (File Menu) Writes All Assignments to a Tcl File Message Window Copyright 169。 2022 Altera Corporation 98 AE Dynamic Checking ? Validity of Constraint Checked during Entry ? ColorCoded to Display Status ? Grey – Disabled ? Black – Applied ? Yellow – Assignment Warning ? Dark Red – Inplete ? Bright Red – Error/Illegal Value ? Green – Enter New Assignment Copyright 169。 Lower Levels of Hierarchy Use Filter to Select the Nodes to Be Displayed Select Nodes on Left amp。 2022 Altera Corporation 96 Editing Multiple Assignments ?Use Edit Bar Editing Multiple I/O Standards at Once Copyright 169。 2022 Altera Corporation 95 Using Assignment Editor Select Assignment from DropDown Menu amp。 Right Clicking Opening Assignment Editor Assignments Menu Copyright 169。 Paste from Clipboard Sort on Columns Enable/Disable Individual Assignments Copyright 169。 2022 Altera Corporation 92 Assignment Editor (AE) ? Provides Spreadsheet Assignment Entry amp。 Elaboration before Obtaining Hierarchy amp。 2022 Altera Corporation 91 Assignments ?Assignment Editor ?Example Assignments ?I/O Assignments amp。 2022 Altera Corporation 90 Register Duplication ?High FanOut Register Is Duplicated amp。 2022 Altera Corporation 88 Physical Synthesis ? ReSynthesis Based on Fitter Output ? Makes Incremental Changes that Improve Results for a Given Placement ? Compensates for Routing Delays from Fitter ? Types ? Combinational Logic ? Registers ? Register Duplication ? Register Retiming ? Effort ? Trades Performance vs Compile Time ? Normal, Extra or Fast Created/Modified Nodes Noted in Compilation Report Copyright 169。 NonCritical Paths ?Makes Changes at Gate Level DQ DQDQ7 n s 8 n sDQ DQDQ10 n s 5 n sCopyright 169。 then Remaps to Altera Primitives ? Unavailable when Using Integrated Synthesis ? Considerations ? Node Names May Change ? 3rdParty Synthesis Attributes May Be Lost ?Preserve/Keep ? Some Registers May Be Synthesized Away Copyright 169。 2022 Altera Corporation 84 Synthesis Netlist Optimizations ?Further Optimize Netlists during Synthesis ?Types ? WYSIWYG Primitive Resynthesis ? GateLevel Register Retiming Created/Modified Nodes Noted in Compilation Report Copyright 169。 2022 Altera Corporation 82 VersionCompatible Database ?Remended ?Exports a Database that Can Be Opened Directly in another Version of Quartus II ? Import Database into New Version ?Two Methods to Create ? Settings Dialog Box ? Project Menu Analyze Previously Compiled Projects Using Updated Timing Models Copyright 169。 2022 Altera Corporation 80 Settings Dialog Box Change Settings ? TopLevel Entity ? Target Device ? Add/Remove Files ? Libraries ?VHDL ?87, ?93? ?Verilog ?95, ?01? ? EDA Tool Settings ? Timing Settings ? Compiler Settings ? Simulator Settings Copyright 169。 Assignments ?Uses Tcl Syntax Organized by Assignment Type Copyright 169。 Constraints) ?Individual Entity/Node Controls ? Accessed Using Assignments Menu ? Stored in QSF File Copyright 169。 2022 Altera Corporation 77 Synthesis amp。 2022 Altera Corporation 75 Several Sections Detail the Resource Usage Resource Usage Copyright 169。 Message Windows Copyright 169。 2022 Altera Corporation 73 ? Status Bars Scroll to Indicate Progress ? Message Window Displays Informational, Warning, amp。 Elaboration or Analysis amp。 2022 Altera Corporation 71 TOP A:inst1 B:inst2 B?:inst2 Incremental Compilation Concept TOP A:inst1 B:inst2 A + B + = B? Only Specified Portions of Logic that Have Changed Are ReSynthesized or ReFitted Choose to Reuse PostSynthesis or PostFit Netlist Copyright 169。 When PreSelected Parts of Design Are Compiled ? Benefits ?Decrease Compilation Time ?Maintain amp。 Synthesis ? Synthesize Code ? Estimate Timing ? Start Fitter ? Start Assembler ? Start Timing Analysis ? Start I/O Assignment Analysis ? Start Design Assistant Processing Options Processing Toolbar Copyright 169。 Elaboration ? Check Syntax amp。 2022 Altera Corporation 68 Quartus II Compilation ?Synthesis ?Fitting ?Generating Output ? Timing Analysis Output Netlist ? Simulation Output Netlists ? Programming/Configuration Output Files Copyright 169。 2022 Altera Corporation 66 Design Entry Summary ?Multiple Design Entry Methods ? Text (Verilog, VHDL, AHDL) ? Third Party Netlist (VQM, EDF) ? Schematic ?Memory Editor ?MegaWizard ?EDA Tool Flows Copyright 169。 2022 Altera Corporation 65 ?Created a Schematic Design ?Generated Logic Using MegaWi