【正文】 s interrupt latency. An EIC is typically used in conjunction with shadow register sets and when you need more than the 32 interrupts provided by the Nios II internal interrupt controller. The Nios II processor connects to an EIC through the EIC interface. When an EIC is present, the internal interrupt controller is not implemented。 hardware implementation or software emulation of a feature. An example of each tradeoff follows: ■ More or less of a feature— For example, to finetune performance, you can increase or decrease the amount of instruction cache memory. A larger cache increases execution speed of large programs, while a smaller cache conserves onchip memory resources. ■ Inclusion or exclusion of a feature— For example, to reduce cost, you can choose to omit the JTAG debug module. This decision conserves onchip logic and memory resources, but it eliminates the ability to use a software debugger to debug applications. ■ Hardware implementation or software emulation— For example, in control applications that rarely perform plex arithmetic, you can choose for the division instruction to be emulated in software. Removing the divide hardware conserves onchip resources but increases the execution time of division operations. For information about which Nios II cores supports what features, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook. For plete details about userselectable parameters for the Nios II processor, refer to the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. Register File The Nios II architecture supports a flat register file, consisting of thirtytwo 32bit generalpurpose integer registers, and up to thirtytwo 32bit control registers. The architecture supports supervisor and user modes that allow system code to protect the control registers from errant applications. The Nios II processor can optionally have one or more shadow register sets. A shadow register set is a plete set of Nios II generalpurpose registers. When shadow register sets are implemented, the CRS field of the status register indicates which register set is currently in use. An instruction access to a generalpurpose register uses whichever register set is active. A typical use of shadow register sets is to accelerate context switching. When shadow register sets are implemented, the Nios II processor has two special instructions, rdprs and wrprs, for moving data between register sets. Shadow register sets are typically manipulated by an operating system kernel, and are transparent to application code. A Nios II processor can have up to 63 shadow register sets. For details about shadow register set implementation and usage, refer to “ Registers” and “ Exception Processing” in the Programming Model chapter of the Nios II Processor Reference Handbook. For details about the rdprs and wrprs instructions, refer to the Instruction Set Reference chapter of the Nios II Processor Reference Handbook. The Nios II architecture allows for the future addition of floatingpoint registers. Arithmetic Logic Unit The Nios II ALU operates on data stored in generalpurpose registers. ALU operations take one or two inputs from registers, and store a result back in a register. Unimplemented Instructions Some Nios II processor core implementations do not provide hardware to support the entire Nios II instruction set. In such a core, instructions without hardware support are known as unimplemented instructions. The processor generates an exception whenever it issues an unimplemented instruction so your exception handler can call a routine that emulates the operation in software. Unimplemented instructions do not affect the programmer’s view of the processor. For a list of potential unimplemented instructions, refer to the Programming Model chapter of the Nios II Processor Reference Handbook. Custom Instructions The Nios II architecture supports userdefined custom instructions. The Nios II ALU connects directly to custom instruction logic,enabling you to implement operations in hardware that are accessed and used exactly like native instructions. For more information, refer to the Nios II Custom Instruction User Guide and “ Custom Instruction Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. FloatingPoint Instructions The Nios II architecture supports single precision floatingpoint instructions as specified by the IEEE Std 7541985. The basic set of floatingpoint custom instructions includes single precision floatingpoint addition, subtraction, and multiplication. Floatingpoint division is available as an extension to the basic instruction set. These floatingpoint instructions are implemented as custom instructions. Table 2– 2lists a detailed description of the conformance to IEEE 7541985. You can add floatingpoint custom instructions to any Nios II processor design. The floatingpoint division hardware requires more resources than the other instructions. The Floating Point Hardware parameter editor allows you to omit the floatingpoint division hardware for cases in which code running on your hardware design does not make heavy use of floatingpoint division. When you omit the floatingpoint divide instruction, the Nios II piler implements floatingpoint division in software. In Qsys, the Floating Point Hardware ponent under Custom Instruction Modules on the Component Library tab contains the floatingpoint custom instructions. To add floatingpoint custom instructions to your Nios II processor core in SOPC Builder, refer to “ Custom Instruction Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. The Nios II floatingpointc