【正文】 s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, e from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is deposited, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 onechip puters, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of . This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other puters, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is manded. There are ROM procedure memory , can only read and RAM in 8051 slices data memory, can is it can write two to read, they have each independent memory address space, dispose way to be the same with general memory of puter. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS51 series onechip puter and general puter disposes the way in addition. General puter for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: 1 In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice use 16 addresses . 2 The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH with 16 addresses too to the location. 3 Data memory address space of 256B use 8 addresses . Three abovementioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 onechip puter have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate twoway mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch namely special function register , one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of pass way these selfsame. Expand among the system of memory outside having slice, four port these may serve as accurate twoway mouth of I/O in mon use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off。你們的鼓勵和幫助永遠是我前進的動力。 致 謝 首先，我要感謝 *************大學，感謝電氣系對我四年的培養(yǎng)，讓我學到了許許多多的知識，感謝各位老師在這四年里對我的關懷與照顧，在此致以我深深的謝意。 LED_G 1。 for t 0。 //取百分比個位（帶小數(shù)點） baifenshu[3] tmp%10。//計算 放大到 0－ 1000 ， 注 意 化 簡 ， 不 然 會 計 算 溢 出 得 不 到 正 確 結(jié) 果 //ad_shuju*1000/255。baifenshu 。 // ADC_OE 0。 //關閉顯示 //端口初始化 P2 0xff。 unsigned char data baifenshu[4]。 P2 P2 | hang[i]。 //關顯示 P2 P2 amp。 //返回結(jié)果 void display unsigned char ptr[] static unsigned char data i。 //等待轉(zhuǎn)換結(jié)束 ADC_OE 1。 //啟動轉(zhuǎn)換 ADC_ALE 0。 i++ 。 //指示燈引腳 sbit LED_G P2^0。 //數(shù)碼管控制引腳 sbit LED2 P2^6。 //AD 采集控制引腳 sbit ADC_STR P3^4。 本設計通過觀察 LED 數(shù)碼顯示器顯示瓦斯?jié)舛戎?，判斷瓦斯?jié)舛戎凳欠癯^上限值，如果超過，自動報警。 P 口為高電位或高阻狀態(tài)發(fā)光管暗的時候電流是從電源正――上拉電阻―― P 口，這時 LED 無電流流過， P 口為低電位，限流電阻上流過電流全部從 P 口流入。 聲光報警單元與單片機的連接 圖如下： 圖 311 聲光報警電路 LED 顯示 LED數(shù)碼顯示器是一種由 LED發(fā)光二極管組合顯示字符的顯示器件。 圖 310 ADC0809 與 AT89C51 接口電路 聲光報警與 LED 顯示 警單元 作為煤氣泄露測試裝置，聲光報警部分不可缺少，當檢測到瓦斯氣體在空氣中的所占的比例超標時，就應該通過聲光方式發(fā)出警報，防止由于瓦斯氣體含量過高而發(fā)生的意外事故。 CPU響應中斷后，應在中斷服務程序中使 OE 線變?yōu)楦唠娖剑蕴崛?A/D轉(zhuǎn)換后的數(shù)字量。 3 要給“三態(tài)輸出鎖存器”分配一個端口地址，也就是給 OE 線上送一個地址譯碼器輸出信號。 用戶還可以采用外部時鐘，在這種情況下，外部時鐘脈沖接到XTAL1 部時鐘發(fā)生器的輸入端， XTAL2 則懸空。在 FLASH 編程期間，此引腳也用于施加 12V 編程電源（ VPP）。在由外部程序存儲器取指期間，每個機器周期兩次 /PSEN 有效。此時， ALE 只有在執(zhí)行 MOVX， MOVC 指令是ALE 才起作用。在平時， ALE 端以不變的頻率周期輸出正脈沖信號，此頻率為振蕩器頻率的