【正文】 當“1”被寫入P0口時，每個管腳都能夠作為高阻抗輸入端。閑散方式停止中央處理器的工作，能夠允許隨機存取數(shù)據(jù)存儲器、定時/計數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。和128字節(jié)的存取數(shù)據(jù)存儲器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲技術生產(chǎn)，并且能夠與MCS51系列的單片機兼容。2個16位定時/計數(shù)器全靜態(tài)操作：0Hz24MHz 10 pF for Ceramic ResonatorsFigure 2. External Clock Drive ConfigurationIdle Mode:In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power Down Mode:In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock Bits:On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:When lock bit 1 is programmed, the logic level at the pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash:The AT89C51 is normally shipped with the onchip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high voltage (12volt) or a lowvoltage (Vcc) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the highvoltage programming mode is patible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the highvoltage or lowvoltage programming mode enabled. The respective topside marking and device signature codes are listed in the following table.Vpp=12VVpp=5VTopSide MarkAT89C51xxxxyywwAT89C51xxxx5yywwSignature(030H)=1EH(031H)=51H(032H)=FFH(030H)=1EH(031H)=51H(032H)=05HThe AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct bination of control signals.4. Raise /Vpp to 12V for the highvoltage programming mode. 5. Pulse ALE/ once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Polling:The AT89C51 features Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Polling may begin any time after a write cycle has been initiated. Ready/: The progress of byte programming can also be monitored by the RDY/ output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper bination of control signals and by holding ALE/ low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming Interface:Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate bination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to pletion.外文資料譯文AT89C51的介紹主要性能參數(shù)：Six Interrupt SourcesThreeLevel Program Memory Lock傳感器技術 2000,19(4):2933[4] 戴梅萼, 史嘉. 微型計算機技術及應用. 北京: 清華大學出版社, 1995[5] 丁元杰. 單片微機原理及應用. 北京: 機械工業(yè)出版社,