【正文】 data:in integer range 0 to 255。use 。END juchi。USE 。END square。USE 。 constant FONT: rom_type := ( 64,65,66,66,67,68,69,69,70,71,72,73,73,74,75,76,76,77,78,79,80,80,81,82,83,83,84,85,86,86,87,88,88,89,90,91,91,92,93,93,94,95,96,96,97,98,98,99,100,100,101,101,102,103,103,104,105,105,106,106,107,108,108,109,109,110,110,111,111,112,112,113,113,114,114,115,115,116,116,117,117,118,118,118,119,119,120,120,120,121,121,122,122,122,123,123,123,123,124,124,124,125,125,125,125,125,126,126,126,126,126,127,127,127,127,127,127,127,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,127,127,127,127,127,127,127,126,126,126,126,126,125,125,125,125,125,124,124,124,123,123,123,123,122,122,122,121,121,120,120,120,119,119,118,118,118,117,117,116,116,115,115,114,114,113,113,112,112,111,111,110,110,109,109,108,108,107,106,106,105,105,104,103,103,102,101,101,100,100,99,98,98,97,96,96,95,94,93,93,92,91,91,90,89,88,88,87,86,86,85,84,83,83,82,81,80,80,79,78,77,76,76,75,74,73,73,72,71,70,69,69,68,67,66,66,65,64,63,62,62,61,60,59,59,58,57,56,55,55,54,53,52,52,51,50,49,48,48,47,46,45,45,44,43,42,42,41,40,40,39,38,37,37,36,35,35,34,33,32,32,31,30,30,29,28,28,27,27,26,25,25,24,23,23,22,22,21,20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,12,12,11,11,10,10,10,9,9,8,8,8,7,7,6,6,6,5,5,5,5,4,4,4,3,3,3,3,3,2,2,2,2,2,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,2,2,2,2,2,3,3,3,3,3,4,4,4,5,5,5,5,6,6,6,7,7,8,8,8,9,9,10,10,10,11,11,12,12,13,13,14,14,15,15,16,16,17,17,18,18,19,19,20,20,21,22,22,23,23,24,25,25,26,27,27,28,28,29,30,30,31,32,32,33,34,35,35,36,37,37,38,39,40,40,41,42,42,43,44,45,45,46,47,48,48,49,50,51,52,52,53,54,55,55,56,57,58,59,59,60,61,62,62,63)。ENTITY rom_sin ISPORT( addr:IN integer range 0 to 511 。fclose(fid)。sin_d])。fprintf(fid,39。)。)。)。fid=fopen(39。 index=linspace(0,2*pi,depth)。add=t(31 downto 23)。 then t=data。 then t=x00000000。end dff32 。 rstn:in std_logic。相位寄存器源程序：library ieee。 addr_out:out std_logic_vector(31 downto 0) )。use 。END IF。 then if LOAD=39。 then DATA=X00000000。 DATA:OUT std_logic_vector(31 downto 0) )。 use 。在四個(gè)月課題研究的日子里，師生間結(jié)下了深厚的情誼。本設(shè)計(jì)采用DDS技術(shù)，克服了傳統(tǒng)方法波形少、不易調(diào)頻的局限，完成了方便調(diào)頻、調(diào)幅的函數(shù)信號(hào)發(fā)生器的設(shè)計(jì)。圖52三角波圖53鋸齒波 方波結(jié)論本設(shè)計(jì)采用自上而下的設(shè)計(jì)方法，詳細(xì)闡述了函數(shù)信號(hào)發(fā)生器的系統(tǒng)設(shè)計(jì)，系統(tǒng)可實(shí)現(xiàn)任意波形和固定波形的輸出。經(jīng)過(guò)反復(fù)試驗(yàn)，分別得到如圖51正弦波，如圖52三角波，如圖53鋸齒波。頻率控制字若較小，則產(chǎn)生波形的周期將會(huì)很大，可能無(wú)法形象的觀察到仿真波形。工程名和頂層實(shí)體名必須完全相同，且不能用中文名稱，否則會(huì)編譯出錯(cuò)。Data：輸入的數(shù)據(jù)Data_out:處理后輸出的數(shù)據(jù)仿真波形圖如下所示：如果輸入的MAX_MIN是高電平，則data_out=data*set，如果是低電平，則data_out=data/set。在軟件工具Quartus II的編譯和波形仿真后得到的波形如圖414所示。 wave: out integer range 0 to 255 )。LIBRARY IEEE。在軟件工具Quartus II的編譯和波形仿真后得到的波形如圖412所示。 wave: out integer range 0 to 255 )。方波模塊功能設(shè)計(jì)的VHDL程序如下：LIBRARY IEEE。在軟件工具Quartus II的編譯和波形仿真后得到的波形如圖410所示。 wave: out integer range 0 to 255 )。方波模塊功能設(shè)計(jì)的VHDL程序如下：LIBRARY IEEE。圖48波形數(shù)據(jù)工作空間中的數(shù)據(jù)如下圖所示：程序進(jìn)行波形仿真結(jié)果如下所示：該模塊主要功能是生成方波波形。 constant FONT: rom_type := ( 128,130,131,133,134,136,137,139,141,142,144,145,147,148,150,151,153,155,156,158,159,161,162,164,165,167,168,170,171,173,174,176,177,178,180,181,183,184,186,187,188,190,191,192,194,195,196,198,199,200,202,203,204,206,207,208,209,210,212,213,214,215,216,217,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,234,235,236,237,238,239,239,240,241,242,242,243,244,244,245,246,246,247,247,248,249,249,250,250,250,251,251,252,252,253,253,253,254,254,254,254,255,255,255,255,255,256,256,256,256,256,256,256,256,256,256,256,256,256,256,256,255,255,255,255,255,254,254,254,254,253,253,253,252,252,251,251,250,250,250,249,249,248,247,247,246,246,245,244,244,243,242,242,241,240,239,239,238,237,236,235,234,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,217,216,215,214,213,212,210,209,208,207,206,204,203,202,200,199,198,196,195,194,192,191,190,188,187,186,184,183,181,180,178,177,176,174,173,171,170,168,167,165,164,162,161,159,158,156,155,153,151,150,148,147,145,144,142,141,139,137,136,134,133,131,130,128,126,125,123,122,120,119,117,115,114,112,111,109,108,106,105,103,101,100,98,97,95,94,92,91,89,88,86,85,83,82,80,79,78,76,75,73,72,70,69,68,66,65,64,62,61,60,58,57,56,54,53,52,50,49,48,47,46,44,43,42,41,40,39,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,22,21,20,19,18,17,17,16,15,14,14,13,12,12,11,10,10,9,9,8,7,7,6,6,6,5,5,4,4,3,3,3,2,2,2,2,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,2,2,2,2,3,3,3,4,4,5,5,6,6,6,7,7,8,9,9,10,10,11,12,12,13,14,14,15,16,17,17,18,19,20,21,22,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,42,43,44,46,47,48,49,50,52,53,54,56,57,58,60,61,62,64,65,66,68,69,70,72,73,75,76,78,79,80,82,83,85,86,88,89,91,92,94,95,97,98,100,101,103,105,106,108,109,111,112,114,115,117,119,120,122,123,125,126)。根據(jù)設(shè)計(jì)，截取相位累加器的高9位作為ROM尋址的位數(shù)。add=t(31 downto 23)。 then t=data。 then t=x00000000。end dff32 。 rstn:in std_logic。相位寄存器模塊功能設(shè)計(jì)的VerilogHDL程序如下：library ieee。CLK：系統(tǒng)時(shí)鐘信號(hào)，頻率為50MHZ.。圖44 32位加法器功能仿真該模塊主要功能是寄存上一次相位累加和，取累加和高9位作為ROM數(shù)據(jù)表的地址。end addr。 use 。data[31..0]：相位寄存器值，保存累加值。相位寄存器將累加和送回加法器輸入端用于下一次計(jì)算，取高8位作為ROM地址，同時(shí)送入鋸齒波模塊、方波模塊和三角波模塊。end one。 THEN DATA=FCW。event and clk=39。ARCHITECTURE one of reg_fcw isBEGIN PROCESS(clk,rstn)begin if rstn=39。 rstn,LOAD:in std_logic。頻率寄存器模塊功能設(shè)計(jì)的VerilogHDL程序如下：library ieee。圖41頻率寄存器模塊結(jié)構(gòu)框圖各端口說(shuō)明如下：Rstn：復(fù)位信號(hào)，低電平有效。此信號(hào)用3位二進(jìn)制表示，當(dāng)max位高電平的時(shí)候進(jìn)行放大，相仿的情況下位縮小。rstn：復(fù)位信號(hào)，低電平有效。如圖39所示，系統(tǒng)共有多個(gè)輸入信號(hào)和1個(gè)輸出信號(hào)。 FPGA系統(tǒng)模塊設(shè)計(jì)系統(tǒng)模塊設(shè)計(jì)如圖38所示。相位累加器高8位作為地址進(jìn)行ROM表查詢，本設(shè)計(jì)ROM表中存儲(chǔ)正弦數(shù)據(jù)，用于生成正弦波形，ROM表中也可存儲(chǔ)其它波形數(shù)據(jù)，生成任意波形。系統(tǒng)的總體硬件結(jié)構(gòu)如圖36所示。設(shè)計(jì)時(shí)分兩大部分進(jìn)行，波形模塊和外圍電路模塊。鋸齒波以DDS相位累加器輸出信號(hào)的高8位為輸入，得到其基本波形。用FPGA可以非常方便的實(shí)現(xiàn)DDS系統(tǒng)的數(shù)字電路環(huán)節(jié)，且可現(xiàn)場(chǎng)編程進(jìn)行電路的修改。因?yàn)?，只要改變FPGA中的ROM數(shù)據(jù)，DDS就可以產(chǎn)生任意波形，因而具有相當(dāng)大的靈活性。近來(lái)，CPLD及FPGA的發(fā)展為實(shí)現(xiàn)DDS提供了更好的技術(shù)手段。，設(shè)置仿真時(shí)間，Edit→End Time打開(kāi)如圖35對(duì)話框。圖33乘法器 Diagram/Sche