【正文】
進(jìn)行硬件驗(yàn)證時(shí)方法如下:選擇實(shí)驗(yàn)?zāi)J?0,測(cè)頻控制器時(shí)鐘信號(hào) CLK與 CLOCK1信號(hào)組中的 1 Hz信號(hào)相接,待測(cè)頻 FSIN與 CLOCK0信號(hào)組中的某個(gè)信號(hào)相接,數(shù)碼管應(yīng)顯示來自CLOCK0的頻率。139。039。 THEN DOUT=DIN; 鎖存輸入數(shù)據(jù) END IF ; END PROCESS; END ART; 3) 測(cè)頻控制信號(hào)發(fā)生器的源程序 LIBRARY IEEE; USE ; 測(cè)頻控制信號(hào)發(fā)生器 USE ENTITY TESTCTL IS PORT (CLK: IN STD_LOGIC; 1 Hz測(cè)頻控制時(shí)鐘 TSTEN: OUT STD_LOGIC; 計(jì)數(shù)器時(shí)鐘使能 CLR_CNT: OUT STD_LOGIC; 計(jì)數(shù)器清零 LOAD: OUT STD_LOGIC); 輸出鎖存信號(hào) END TESTCTL; ARCHITECTURE ART OF TESTCTL IS SIGNAL Dvi2CLK : STD_LOGIC; BEGIN PROCESS ( CLK ) BEGIN IF CLK39。039。139。 THEN CQI= 0; 計(jì)數(shù)器異步清零 ELSIF CLK39。 3) 十進(jìn)制計(jì)數(shù)器 CNT10的設(shè)計(jì) 如圖所示,此十進(jìn)制計(jì)數(shù)器的特殊之處是,有一時(shí)鐘使能輸入端 ENA, 用于鎖定計(jì)數(shù)值。由圖可見,在計(jì)數(shù)完成后,即計(jì)數(shù)使能信號(hào) TSTEN在 1 s的高電平后,利用其反相值的上跳沿產(chǎn)生一個(gè)鎖存信號(hào) LOAD, s后, CLR_CNT產(chǎn)生一個(gè)清零信號(hào)上跳沿。測(cè)頻控制信號(hào)發(fā)生器的工作時(shí)序如圖所示。這就要求 TESTCTL的計(jì)數(shù)使能信號(hào) TSTEN能產(chǎn)生一個(gè) 1秒脈寬的周期信號(hào),并對(duì)頻率計(jì)的每一計(jì)數(shù)器 CNT10的 ENA使能端進(jìn)行同步控制。 END IF; END IF; END PROCESS; PROCESS( reset ,clk ) 定時(shí)器 ST BEGIN IF( reset = ′0′ ) THEN ST = ′0′; ELSIF( clk′EVENT AND clk = ′1′ ) THEN IF( Q = 2 )THEN ST = ′1′; ELSE ST = ′0′; END IF; END IF; END PROCESS; END ARCHITECTURE arch; 控制器模塊( ): LIBRARY IEEE; USE ; USE ; ENTITY control IS PORT( reset ,clk ,ST ,Ca ,Cb : IN STDLOGIC; Ra ,Ya ,Ga ,Rb ,Yb ,Gb ,LD : OUT STDLOGIC; CNT : OUT INTEGER RANGE 0 TO 63 ); END ENTITY control; ARCHITECTURE arch OF control IS CONSTANT T1 : INTEGER : = 60; CONSTANT T2 : INTEGER : = 40; CONSTANT T3 : INTEGER : = 10; TYPE STATETYPE IS ( S0 ,S1 ,S2 ,S3 ); SIGNAL state : STATETYPE; SIGNAL RYG : STDLOGICVECTOR( 5 DOWNTO 0 ); BEGIN PROCESS( reset ,clk ) BEGIN IF( reset = ′0′ ) THEN state = S0; ELSIF( clk′EVENT AND clk = ′1′ ) THEN IF( ST = ′1′ ) THEN CASE state IS WHEN S0 = IF( Cb = ′0′) THEN state = S0; ELSE state = S1; END IF; WHEN S1 = state = S2;