【正文】 圓圈里的數(shù)代表發(fā)送器和接收器的時(shí)序位。數(shù)據(jù)發(fā)送器和接收器必須在事務(wù)開(kāi)始時(shí)同步它們的時(shí)序位。這種機(jī)制提供一種保證發(fā)送器和接收器正確地解釋事務(wù)的握手時(shí)相的方法。 當(dāng)一個(gè)節(jié)點(diǎn)正在為中斷一個(gè)數(shù)據(jù)而使用中斷傳輸工程時(shí)，必須要使用數(shù)據(jù)的固定協(xié)議。如果端口沒(méi)有出現(xiàn)新的中斷信息（即沒(méi)有中斷正在等待）此功能部件返回一個(gè) NAK握手信號(hào)在數(shù)據(jù)階段。例 如，如果數(shù)據(jù)階段是一個(gè)輸出事務(wù)構(gòu)成，狀態(tài)是一個(gè)的輸入事務(wù)。如果數(shù)據(jù)量超過(guò)了此前確定的數(shù)據(jù)包大小，數(shù)據(jù)在支持最大的包的多個(gè)事務(wù)中被發(fā)送（輸入或者輸出）。如果數(shù)據(jù)已經(jīng)損壞了，就要隨機(jī)放棄此數(shù)據(jù)并 且不要回饋交互數(shù)據(jù)。在建立這個(gè)過(guò)程中，特別專(zhuān)注于信息傳輸控制閘口的服務(wù)。如果主機(jī)收 到合法的的數(shù)據(jù)包，則它使用 ACK握手?jǐn)?shù)據(jù)包作為應(yīng)答。在某些流控制和掛起條件下，數(shù)據(jù)時(shí)相被握手信號(hào)替換，從而產(chǎn)生了沒(méi)有數(shù)據(jù)傳輸?shù)膬上嗟氖聞?wù)。這節(jié)的剩下的部分將提到功能 STALL的一般情況。如果一個(gè)功能部件的端口被掛起，那么功能部件必須繼續(xù)返回 STALL，直到掛起通過(guò)主機(jī)干涉被清除。在任何情況下都 不允許主機(jī)返回 STALL。 NAK用于流控制的目的是，表示功能部件暫時(shí)不能發(fā)送或接收數(shù)據(jù)，但是最終還是能夠在不需主機(jī)干涉的情況下發(fā)送或接收數(shù)據(jù)； 3)STALL被一個(gè)功能部件送回作為一個(gè)輸入標(biāo)記的回應(yīng)。 ACK握手信號(hào)只在數(shù)據(jù)被傳送并且期待握手信號(hào)時(shí)適用。在傳輸一個(gè)字節(jié)的數(shù)據(jù)包后，交互數(shù)據(jù)包可以無(wú)限的以EOP的形式傳輸。全速設(shè)備 不被總線時(shí)間調(diào)配信息的沒(méi)有特別需要，可以忽略 SOF包。 SOF包發(fā)送 2個(gè)時(shí)間調(diào)配信息。幀開(kāi)始包是由 指示包類(lèi)型的 PID和其后的 11位的幀號(hào)字段 組成 ，如圖 86中所示。 幀開(kāi)始包 幀開(kāi)始包是由主機(jī) 按 額定速率發(fā)出 的，對(duì)于 全速總線，以每 ms 177。 圖 85 標(biāo)記包格式 如上圖所示，標(biāo)記包由 5位 CRC組成包括覆蓋地址和端口字段。只有主機(jī)可以發(fā)送標(biāo)記包。 對(duì)于 輸出和建立事務(wù)，地址 和端口字段唯一地確定了接下來(lái)將收到數(shù)據(jù)包的端口。所有的數(shù)據(jù)包都有明顯的 包的啟動(dòng) 和結(jié)束分隔符。在同步設(shè)置中，最后兩個(gè) 字節(jié)為定義同步區(qū)域的結(jié)束，或者相反地，也可以定義起始。這是用來(lái)使電路的輸入數(shù)據(jù)可以與本地?cái)?shù)據(jù)同步。 they support endtoend data integrity using error detection and retry. Isochronous transactions, by virtue of their bandwidth and latency requirements, do not permit retries and must tolerate a higher incidence of uncorrected errors. Neither the device nor the host will send an indication that a received packet had an error. This absence of positive acknowledgement is considered to be the indication that there was an error. As a consequence of this method of error reporting, the host and USB function need to keep track of how much time has elapsed from when the transmitter pletes sending a packet until it begins to receive a response packet. This time is referred to as the bus turnaround time. Devices and hosts require turnaround timers to measure this time. For full/lowspeed transactions, the timer starts counting on the SE0to?J? transition of the EOP strobe and stops counting when the Idleto?K? SOP transition is detected. For highspeed transactions, the timer starts counting when the data lines return to the squelch level and stops counting when the data lines leave the squelch level. The device bus turnaround time is defined by the worst case round trip delay plus the maximum device response delay. If a response is not received within this worst case timeout, then the transmitter considers that the packet transmission has failed. Timeout is used and interpreted as a transaction error condition for many transfer types. If the host wishes to indicate an error condition for a transaction via a timeout, it must wait the full bus turnaround time before issuing the next token to ensure that all downstream devices have timed out. False EOPs must be handled in a manner which guarantees that the packet currently in progress pletes before the host or any other device attempts to transmit a new packet. If such an event were to occur, it would constitute a bus collision and have the ability to corrupt up to two consecutive transactions. Detection of false EOP relies upon the fact that a packet into which a false EOP has been inserted will appear as a truncated packet with a CRC failure. (The last 16 bits of the data packet will have a very low probability of appearing to be a correct CRC.) 14 The host and devices handle false EOP situations differently. When a device receives a corrupted data packet, it issues no response and waits for the host to send the next token. This scheme guarantees that the device will not attempt to return a handshake while the host may still be transmitting a data packet. If a false EOP has occurred, the host data packet will eventually end, and the device will be able to detect the next token. If a device issues a data packet that gets corrupted with a false EOP, the host will ignore the packet and not issue the handshake. The device, expecting to see a handshake from the host, will timeout the transaction. If the host receives a corrupted full/lowspeed data packet, it assumes that a false EOP may have occurred and waits for 16 bit times to see if there is any subsequent upstream traffic. If no bus transitions are detected within the 16 bit interval and the bus remains in the Idle state, the host may issue the next token. 15 二、譯文 協(xié)議層 排 序 當(dāng) 數(shù)據(jù)位被發(fā)送到總線的時(shí)，首先 發(fā)送的是最低有效位 ，跟著 發(fā)送的是 下一個(gè)最低有效位，最后 發(fā)送的是 最重要的有效位。 五、進(jìn)度計(jì)劃 1 周：完成開(kāi)題報(bào)告 24 周：完成基本電路設(shè)計(jì) 510 周：調(diào)試、修改 1112 周：英文翻譯及論文 13 周：論文 修改裝訂，準(zhǔn)備答辯 14 周：答辯 6 大學(xué)畢業(yè)設(shè)計(jì)（論文）外文原文及譯文 題目： 數(shù)據(jù)記錄儀 — 總體方案設(shè)計(jì)及顯示電路、軟件 專(zhuān)業(yè)： 指導(dǎo)教師： 學(xué)院： 學(xué)號(hào)： 班級(jí)： 姓名： 一、 外文原文 出處： Protocol Layer Byte/Bit Ordering Bits are sent out onto the bus leastsignificant bit (LSb) first, followed by the next LSb, through to the mostsignificant bit (MSb) last. In the following diagrams, packets are displayed such that both individual bits and fields are represented (in a left to right reading order) as they would move across the bus. Multiple byte fields in standard descriptors, requests, and responses are interpreted as and moved over the bus in littleendian order, ., LSB to MSB. SYNC Field All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a maximum edge transition density. It is used by the input circuitry to align ining data with the local clock. A SYNC from an initial transmitter is defined to be eight bits in length for full/lowspeed and 32 bits for highspeed. Received SYNC fields may be shorter as described in Chapter 7. SYNC serves only as a synchronization mechanism and is not shown in the following packet diagrams. The last two bits in the SYNC field are a marker that is used to identify the end of the SYNC field and, by inference, the start of the PID. Packet Field Formats Field for