【正文】 {if(k1num)dx_pass()。if(k2num)nb_pass()。}break。case 1:R1=1。Y1=1。G1=1。//調(diào)整時(shí)間時(shí)，關(guān)閉所有燈R2=1。Y2=1。G2=1。if(tled_display(100,nb_time)。elseled_display(dx_time,nb_time)。break。case 2:R1=1。Y1=1。G1=1。//調(diào)整時(shí)間時(shí)，關(guān)閉所有燈R2=1。Y2=1。G2=1。if(tled_display(dx_time,100)。elseled_display(dx_time,nb_time)。break。}break。}}} } void timer0()interrupt 1 { TH0=(6553650000)/256。TL0=(6553650000)%256。t++。if(t==20){t=0。if(flag_t==0)pass_time。//調(diào)整時(shí)間時(shí)，不執(zhí)行此操作} } void timer1()interrupt 3 { TH1=(6553650000)/256。TL1=(6553650000)%256。t1++。if(t1==20){t1=0。y_time。//單方向通行時(shí)，黃燈閃爍時(shí)間。} }第五篇：FPGA交通燈實(shí)驗(yàn)報(bào)告交通燈實(shí)驗(yàn)報(bào)告一，實(shí)驗(yàn)?zāi)康膶?shí)現(xiàn)兩路信號(hào)燈交替亮起，并利用兩組數(shù)碼管分別對(duì)兩路信號(hào)進(jìn)行倒計(jì)時(shí)。兩路信號(hào)時(shí)間分別為：V:綠燈（30S）H:紅燈（35S）黃燈（5s）綠燈（30S）紅燈（35S）黃燈（5S）二，實(shí)驗(yàn)步驟 建立工程可在歡迎界面點(diǎn)擊“Creat a New Project”進(jìn)入工程建立界面，亦可關(guān)閉歡迎界面，點(diǎn)擊菜單欄的“File”，點(diǎn)擊“New Project Wizard”進(jìn)入建立工程界面。右側(cè)為建立工程界面，點(diǎn)擊next。在此界面選定工程路徑，取好工程名，點(diǎn)擊“Next”。注意：路徑中不能有中文，工程名也不能有中文。一直點(diǎn)擊“Next”進(jìn)入器件設(shè)置界面，DE270開(kāi)發(fā)工具采用的Cyclone II系列的EP2C70F896C6N。點(diǎn)擊“Finish”，完成工程建立點(diǎn)擊“File”，點(diǎn)擊“New” 選擇“Verilog HDL” 2，點(diǎn)擊主界面工具欄中的 選擇“Verilog HDL”寫(xiě)入verilog代碼。代碼如下：module traffic(Clk_50M,Rst,LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V,Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL,led15)。parameter S1=239。b00。parameter S2=239。b01。parameter S3=239。b10。parameter S4=239。b11。input Clk_50M,Rst。output LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V。output[6:0] Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL。output led15。//div for 1Hzstartreg Clk_1Hz。reg [31:0] Cnt_1Hz。always@(posedge Clk_50M or negedge Rst)beginif(!Rst)beginCnt_1HzClk_1Hzendelsebeginif(Cnt_1Hz=25000000)end//div for 1Hzendreg[7:0] Cnt30,CntH,CntV,CntHH,CntVV。reg[7:0] CntDis,CntDiss。//30 counter and seg7startreg LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V。always@(posedge Clk_1Hz)beginendbeginCnt_1HzClk_1HzendelseCnt_1Hzcase(state)S1:endalways@(posedge Clk_1Hz)begincase(stateV)S1:beginif(CntV=30)CntVbeginif(Cnt30=30)Cnt30elseCnt30beginif(Cnt30=5)Cnt30elseCnt30beginif(Cnt30=30)Cnt30elseCnt30beginif(Cnt30=5)Cnt30elseCnt30elseCntVS2: beginendend if(CntV=5)CntVelseCntVS3:beginif(CntV=35)CntVelseCntVcase(stateH)S1:endalways@(negedge Clk_50M or negedge Rst)beginbeginif(CntH=35)CntHelseCntHS2:beginif(CntH=30)CntHelseCntHS3:beginif(CntH=5)CntHelseCntHcase(state)S1:end always@(negedge Clk_50M or negedge Rst)begincase(state)S1:end//16進(jìn)制計(jì)數(shù)器轉(zhuǎn)換為用于顯示的10進(jìn)制計(jì)數(shù)器 always@(posedge Clk_50M)beginif(CntVV29)beginCntDis[7:4]CntDis[3:0]9)beginCntDis[7:4]CntDis[3:0]19)beginCntDiss[7:4]CntDiss[3:0]CntDissendif(Cnt30=5)endend S3:beginstateend S4:beginstateend default:beginstateend endcaseif(Cnt30=30)if(Cnt30=5)always@(posedge Clk_1Hz)begincase(state)S1:endalways@(posedge Clk_50M or negedge Rst)beginstateHstateVend S2:beginstateHstateVend S3:beginstateHstateVend S4:beginstateHstateVend endcase beginif(!Rst)beginLedR_HelseLedG_HLedR_VLedG_Vbegincase(state)S1:beginLedR_HS2:beginLedR_HS3:beginLedR_HS4:begin LedR_HendLedY_Hdefault:beginend LedR_Hendcase assign led15=state。endmodulemodule SEG7_LUT input [3:0] iDIG。output regalways @(iDIG)begincase(iDIG)439。h1: oSEG = 739。b1111001。//t439。h2: oSEG = 739。b0100100。// || 439。h3: oSEG = 739。b0110000。// lt rt439。h4: oSEG = 739。b0011001。// || 439。h5: oSEG = 739。b0010010。//m439。h6: oSEG = 739。b0000010。// || 439。h7: oSEG = 739。b1111000。// lb rb 439。h8: oSEG = 739。b0000000。// || 439。h9: oSEG = 739。b0011000。//b439。ha: oSEG = 739。b0001000。439。hb: oSEG = 739。b0000011。439。hc: oSEG = 739。b1000110。439。hd: oSEG = 739。b0100001。439。he: oSEG = 739。b0000110。[6:0] oSEG。[6:0] oSEG。(oSEG,iDIG)。end439。hf: oSEG = 739。b0001110。439。h0: oSEG = 739。b1000000。endcase endmodule 編譯工程保存文件，將文件放在所建工程所在路徑下 點(diǎn)擊主界面工具欄中的圖標(biāo)也可點(diǎn)擊菜單欄中“Processing”，點(diǎn)擊“Start Compilation”分配關(guān)鍵如下：Clk_50M Input PIN_AD15 LedG_H Output PIN_AD9 LedG_V Output PIN_AJ6 LedR_H Output PIN_AJ7)LedR_V Output PIN_AJ5)LedY_H Output PIN_AD8 LedY_V Output PIN_AK5 Rst Input PIN_AA23 Seg7_HH[6] Output PIN_G1 Seg7_HH[5] Output PIN_H3 Seg7_HH[4] Output PIN_H2 Seg7_HH[3] Output PIN_H1 Seg7_HH[2] Output PIN_J2 Seg7_HH[1] Output PIN_J1 Seg7_HH[0] Output PIN_K3Seg7_HL[6] Seg7_HL[5] Seg7_HL[4] Seg7_HL[3] Seg7_HL[2] Seg7_HL[1] Seg7_HL[0] Seg7_VH[6] Seg7_VH[5] Seg7_VH[4] Seg7_VH[3] Seg7_VH[2] Seg7_VH[1] Seg7_VH[0] Seg7_VL[6] Seg7_VL[5] Seg7_VL[4] Seg7_VL[3] Seg7_VL[2] Seg7_VL[1] Seg7_VL[0] Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output PIN_E4 PIN_F4 PIN_G4 PIN_H8 PIN_H7 PIN_H4 PIN_H6 PIN_AD17 PIN_AF17 7 PIN_AE17 7 PIN_AG16 PIN_AF16 7 PIN_AE16 7 PIN_AG13 PIN_AD12 PIN_AD11 PIN_AF10 8 PIN_AD10 PIN_AH9 8 PIN_AF9 8 PIN_AE8 8燒寫(xiě)代碼在管腳配置完成后，還需將工程再編譯一次，成功后，點(diǎn)擊主界面工具欄中的亦可點(diǎn)擊主界面菜單欄中“Tools”，點(diǎn)擊“Programmer”進(jìn)入代碼燒寫(xiě)界面后，點(diǎn)擊“Start”，當(dāng)“Progress”為100%時(shí)，表示燒寫(xiě)完成，這是可觀(guān)察DE270板現(xiàn)象獲得預(yù)期的效果，兩組的信號(hào)紅黃綠燈交替切換，計(jì)數(shù)器記為零時(shí)信號(hào)燈切換狀態(tài)，紅燈35s，黃燈5s，綠燈30s。三，心得體會(huì)通過(guò)本次實(shí)驗(yàn)初步了解了EDA技術(shù)，熟悉了FPGA開(kāi)發(fā)板的開(kāi)發(fā)流程，鍛煉了動(dòng)手能力。