【導讀】專業(yè)電氣工程及其自動化姓名。們經?？梢栽谏虉鰧W校大樓等公共場所見到的火災報警器火災自動報警系統(tǒng)通。號后立即發(fā)出聲光報警并打開消防聯動裝置本設計的檢測裝置由氣體傳感器溫。度傳感器和與之配套的專用集成電路等組成通過對現場的火災參數采集模數轉。換地址編碼然后傳送給單片機由單片機進行相應的運算處理判斷現場是否發(fā)生?；馂倪@種信號處理方式將單片機用于火災模式判別可以根據火災發(fā)生時火災參。數的發(fā)展變化規(guī)律來識別真假火災不同于傳統(tǒng)單一的定值判別方式有利于提高。與應用至關重要作為整個系統(tǒng)的底層支持其必然向微型化高度集成化網絡化節(jié)。構造火災智能無線報警系統(tǒng)將有廣闊的應用前景。39報警器故障自診斷21. 44線性化子程序24. 46鍵盤處理子程序27. 惡性火災導致的多起群死群傷事件已引起有關部門的高度重視高層賓館大型商。集中且處于長期運行狀態(tài)電氣設備過載過熱短路的火災隱患較多另外由于此類。而生尤其是火災多元復合探測技術在火災探測領域得到廣泛采用如采

　　

【正文】 nable must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VCC for internal program executions This pin also receives the 12volt programming enable voltage VPP during Flash programming XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2Output from the inverting oscillator amplifier Program Memory If the pin is connected to GND all program fetches are directed to external memory On the AT89S52 if is connected to VCC program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2021H through FFFFH are to external memory Data Memory The AT89S52 implements 256 bytes of onchip RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space Instructions which use direct addressing access the SFR space For example the following direct addressing instruction accesses the SFR at location 0A0H which is P2 MOV 0A0H data Instructions that use indirect addressing access the upper 128 bytes of RAM For example the following indirect addressing instruction where R0 contains 0A0H accesses the data byte at address 0A0H rather than P2 whose address is 0A0H MOV R0 data Note that stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack space Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets The WDT consists of a 14bit counter and the Watchdog Timer Reset WDTRST SFR The WDT is defaulted to disable from exiting reset To enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled it will increment every machine cycle while the oscillator is running The WDT timeout period is dependent on the external clock frequency There is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT overflows it will drive an output RESET HIGH pulse at the RST pin In Powerdown mode the oscillator stops which means the WDT also stops While in Powerdown mode the user does not need to service the WDT There are two methods of exiting Powerdown mode by a hardware reset or via a levelactivated external interrupt which is enabled prior to entering Powerdown mode When Powerdown is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89S52 is reset Exiting Powerdown with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Powerdown mode To ensure that the WDT does not overflow within a few states of exiting Powerdown it is best to reset the WDT just before entering Powerdown mode Before going into the IDLE mode the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled The WDT keeps counting during IDLE WDIDLE bit 0 as the default state To prevent the WDT from resetting the AT89S52 while in IDLE mode the user should always set up a timer that will periodically exit IDLE service the WDT and reenter IDLE mode With WDIDLE bit enabled the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE Timer 0 and 1 Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52 For further information on the timers operation please click on the document link below dynresourcesprod_documentsDOC4316PDF Timer 2 Timer 2 is a 16bit TimerCounter that can operate as either a timer or an event counter The type of operation is selected by bit C in the SFR T2CON Timer 2 has three operating modes capture autoreload up or down counting and baud rate generator The modes are selected by bits in T2CON as shown in Table 61 Timer 2 consists of two 8bit registers TH2 and TL2 In the Timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 112 of the oscillator frequency Table3 Timer 2 Operating Modes RCLK TCLK CP TR2 MODE 0 0 1 16bit Autoreload 0 1 1 16bit Capture 1 X 1 Baud Rate Generator X X 0 Off In the Counter function the register is incremented in response to a 1to0 transition at its corresponding external input pin T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the