【導讀】非常重要的技術(shù)。但在某些應用領(lǐng)域中，要求測量溫度用的傳感器不能與被。測物體相接觸，這就需要一種非接觸的測溫方式來滿足上述測溫需求。文正是應上述實際需求而設(shè)計的紅外測溫儀。與傳統(tǒng)的測溫方式相比，具有響應時間短、非接觸、不干擾。被測溫場、使用壽命長、操作方便等一系列優(yōu)點。單片機為其核心控制部件的紅外測溫系統(tǒng)。詳細介紹了該系統(tǒng)的構(gòu)成和實現(xiàn)。方式，給出了硬件原理圖和軟件的設(shè)計流程圖。電探測器、顯示輸出等部分組成。光學系統(tǒng)匯集其視場內(nèi)目標的紅外輻射能。量，紅外能量聚焦在光電探測儀上并轉(zhuǎn)變?yōu)橄鄳碾娦盘枴Ｓ嬎愠瞿繕说臏囟戎翟偻ㄟ^LED把結(jié)果顯示出來。§顯示程序模塊......

　　

【正文】 he crystal encased in the inner oven, and the temperature control circuitry and the inner oven encased in the outer oven. Such oscillators provide even better temperature stability the Oven Controlled Oscillators. Obviously, as the frequency stability improves, the cost of the oscillator increases. Voltage Controlled Oscillator 32 The output of Voltage Controlled Oscillators (VCO) is controlled by a voltage control input pin. Variation between control voltage and frequency is usually nonlinear over the entire frequency range but is linear within subset ranges. Frequency Synthesizers Frequency Synthesizers use one or more PhaseLocked Loops (PLL) to generate one to many different frequencies on their outputs, from one or more reference sources. The reference frequency is usually generated by a crystal attached to the synthesizer. The design goal of frequency synthesizers is to replace multiple oscillators in a system, and hence reduce board space and cost. Figure 1 shows a block diagram of a Phase Locked Loop (PLL). “ Q ”C o u n t e rP h a s e /F r e q u e n c yD e t e c t o rC h a r g eP u m p“ N ”P o s tD i v i d e rL o o pF i l t e rV C O“ P ”C o u n t e rF r e f / QF v c o / PU pD nI c t r l V c t r l F v c o F v c o / NF o u tv c or e fP L L C o u n t r o l S e c t i o n Figure 1 Block Diagram of a Phase Locked Loop A PLL has two inputs, a reference input and a feedback input. A PLL corrects frequency in two ways. The first , frequency correction, corrects large differences in frequency between the reference input and the feedback input. Frequency correctint is akin to “rough” tunint and occurs when Fvco is less than or greater than 2 Fref. Phase correction is the “fine” tuning and occurs when Fvco Fref2 Fvco. The Phase/Frequency Detector detects differences in phase and frequency beween the reference and feedback inputs and generates pensating “Up” and “Down” signals depending on whether the feedback frequency is lagging or leading the reference frequency respectively. These control signals are then passed through a charge pump and a loop filter to generate a conrrol voltage, which controls a VCO. The frequency of this oscillator is dependent on the Vctrl input. At steady state, the VCO frequency is: 33 Fvco= Fref P/Q The output frequency of the PLL can be expressed as Fout=( Fref P)/(Q N) The Sample Rate of a Frequency Synthesizer determines how often the inputs ate sampled in order to perform phase and frequency correctoin. It is expressed as Fref/Q. The Acquisition /Lock Time of a PLLbased Frequency Synthsizer is the amount of time taken by the Frequency Synthesizer to attain the target frequency after powerup, or after a programmed output frequency change. The Resolution of a PLLbased Frequency Synthesizer is base on the number of bits in the P and Q counter. The Resolution will determine in what size increments the frequency can change. The Deadband of a PLLbased Frequency Synthesizer is the largest phase difference between the reference and the feedback inputs, which will not be corrected by the PLL. Multiple PLLs are needed within a single frequency synthesizer to generate multiple unrelated frequencies. Frequency synthesizers are gaining in popularity as system plexity increases and systems utilize multiple clocks. The term “Clock Generator” is interchangeably used wit “Frequency Synthesizer.” Clock Buffers A Clock Buffer is a device in which the output waveform directly follows the input waveform. The input waveform propagates through the device and is redriven by the output buffers. Hence, such devices have a propahation delay associated with them. In addition, due to the differences between the propagation delay through the device on each inputoutput path, skew will exist on the outputs. Clock Parameters Clock Jitter Jitter can be defined as the deviations in a clocl’s output transitions from their ideal positions. The deviation can either be leading or lagging the ideal position. Hence, jitter is expressed in 177。 ns. Jitter can be classified into three categories: cyclecycle jitter, period jetter, and longterm jitter. Cyclecycle jitter is the difference in a clocl’s period from one cycle to the next. 34 This kind of jitter is the most difficult to measure and usually requires a Tining Interval Analyzer. Period jitter, also called shortterm jitter, is a change in a clock’s output transition from its ideal position over consecutive clock edges. Note that in the case of shortterm jitter, the variation of the rising edge of clock from the ideal positon is measured and expressed in units of time or frequrncy. Longterm jitter is a change in a clock’s output transition from its ideal position over “many” cycles. The term ”many” depends on the application and the frequency. For PC motherboard and graphics applications, this term “many” usually refers to 1020 microseconds. For other applications, it may be different. Causes of Jitter There are four primary causes of jitter as indicated below: Power supply noise The internal PLL of the synthesizer Random thermal noise from crystal, or any other resonating device. Random mechanical noise from vibrations of the crystal Clock jitter affects almost all highspeed synchronous systems. Common applications affected by jitter are PC motherboards, graphics cards, and munications equipment. Skew Skew is the variation in arrival time of two signals specified to arrive at the same time. Skew is posed of two parts, the output skew of the driving device, and board design skew, caused by layout variation of board traces. Clock Driver Skew (Intrinsic Skew) is the amount of sk