【導(dǎo)讀】畢業(yè)設(shè)計（論文）89C51單片機和DS18B20數(shù)字溫度計。該AT89S51是一個低功耗高性能CMOS8位微控制器可在4K字節(jié)的系統(tǒng)內(nèi)編。程的閃存存儲器該設(shè)備是采用Atmel的高密度非易失性存儲器技術(shù)和符合工業(yè)。標準的80C51指令集和引腳芯片上的Flash程序存儲器在系統(tǒng)中可重新編程或常。規(guī)非易失性內(nèi)存編程通過結(jié)合通用8位中央處理器的系統(tǒng)內(nèi)可編程閃存的單芯。片AT89S51是一個功能強大的微控制器提供了高度靈活的和具有成本效益的解。在AT89S51提供以下標準功能4K字節(jié)的Flash閃存128字節(jié)的RAM32. 個IO線看門狗定時器兩個數(shù)據(jù)指針兩個16位定時器計數(shù)器5向量兩級中斷。結(jié)構(gòu)全雙工串行端口片上振蕩器和時鐘電路此外AT89S51設(shè)計了可降至零頻率。統(tǒng)繼續(xù)運行掉電模式保存RAM中的內(nèi)容停止振蕩器工作并禁止其它所有部件工。Flash編程時PO端口接收指令字節(jié)而在程序校驗時輸出指令字節(jié)同時要求外接。以避免WDT計數(shù)溢出14位WDT計數(shù)器達到163833FFFHWDT將溢出并使用器件復(fù)。AT89S51共有五個中斷向量兩個外部中斷INT0和INT1兩個定時器中

　　

【正文】 bus MUST be left in the idle state if the transaction is to resume Infinite recovery time can occur between bits so long as the 1Wire bus is in the inactive high state during the recovery period If this does not occur and the bus is left low for more than 480 s all ponents on the bus will be reset HARDWARE CONFIGURATION TRANSACTION SEQUENCE The protocol for accessing the DS18B20 via the 1Wire port is as follows _ Initialization _ ROM Function Command _ Memory Function Command _ TransactionData INITIALIZATION All transactions on the 1Wire bus begin with an initialization sequence The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse s transmitted by the slave s The presence pulse lets the bus master know that the DS18B20 is on the bus and is ready to operate For more details see the 1Wire Signaling section ROM FUNCTION COMMANDS Once the bus master has detected a presence it can issue one of the five ROM function mands All ROM function mands are 8 bits long A list of these mands follows refer to flowchart in Figure 5 Read ROM [33h] This mand allows the bus master to read the DS18B20s 8bit family code unique 48bit serial number and 8bit CRC This mand can only be used if there is a single DS18B20 on the bus If more than one slave is present on the bus a data collision will occur when all slaves try to transmit at the same time open drain will produce a wired AND result Match ROM [55h] The match ROM mand followed by a 64bit ROM sequence allows the bus master to address a specific DS18B20 on a multidrop bus Only the DS18B20 that exactly matches the 64bit ROM sequence will respond to the following memory function mand All slaves that do not match the 64bit ROM sequence will wait for a reset pulse This mand can be used with a single or multiple devices on the bus Skip ROM [CCh] This mand can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64bit ROM code If more than one slave is present on the bus and a Read mand is issued following the Skip ROM mand data collision will occur on the bus as multiple slaves transmit simultaneously open drain pulldowns will produce a wired AND result Search ROM [F0h] When a system is initially brought up the bus master might not know the number of devices on the 1Wire bus or their 64bit ROM codes The search ROM mand allows the bus master to use a process of elimination to identify the 64bit ROM codes of all slave devices on the bus Alarm Search [ECh] The flowchart of this mand is identical to the Search ROM mand However the DS18B20 will respond to this mand only if an alarm condition has been encountered at the last temperature measurement An alarm condition is defined as a temperature higher than TH or lower than TL The alarm condition remains set as long as the DS18B20 is powered up or until another temperature measurement reveals a nonalarming value For alarming the trigger values stored in EEPROM are taken into account If an alarm condition exists and the TH or TL settings are changed another temperature conversion should be done to validate any alarm conditions Example of a ROM Search The ROM search process is the repetition of a simple threestep routine read a bit read the plement of the bit then write the desired value of that bit The bus master performs this simple threestep routine on each bit of the ROM After one plete pass the bus master knows the contents of the ROM in one device The remaining number of devices and their ROM codes may be identified by additional passes The following example of the ROM search process assumes four different devices are connected to the same 1Wire bus The ROM data of the four devices is as shown ROM1 00110101 ROM2 10101010 ROM3 11110101 ROM4 00010001 The search process is as follows 1 The bus master begins the initialization sequence by issuing a reset pulse The slave devices respond by issuing simultaneous presence pulses 2 The bus master will then issue the Search ROM mand on the 1Wire bus 3 The bus master reads a bit from the 1Wire bus Each device will respond by placing the value of the first bit of their respective ROM data onto the 1Wire bus ROM1 and ROM4 will place a 0 onto the 1Wire bus ie pull it low ROM2 and ROM3 will place a 1 onto the 1Wire bus by allowing the line to stay high The result is the logical AND of all devices on the line therefore the bus master sees a 0 The bus master reads another bit Since the Search ROM data mand is being executed all of the devices on the 1Wire bus respond to this second read by placing the plement of the first bit of their respective ROM data onto the 1Wire bus ROM1 and ROM4 will place a 1 onto the 1Wire allowing the line to stay high ROM2 and ROM3 will place a 0 onto the 1Wire thus it will be pulled low The bus master again observes a 0 for the plement of the first ROM data bit The bus master has determined that there are some devices on the 1Wire bus that have a 0 in the first position and others that have a 1 The data obtained from the two reads of the threestep routine have the following interpretations 4 The bus master writes a 0 This deselects ROM2 and ROM3 for the remainder of this search pass leaving only ROM1 and ROM4 connected to the 1Wire bus 5 The bus master performs two more reads and receives a 0bit followed by a 1bit This indicates that all devices still coupled to the bus have 0s as their second ROM data bit 6 The bus master then writes a 0 to keep both ROM1 and ROM4 coupled 7 The bus master executes two reads and receives two 0bits This indicates that both 1bits and 0bits exist as the 3rd bit of the ROM data of the attached devices 8 The bus master writes a 0bit This deselects ROM1 lea