【正文】 *****************************************//*函數(shù)功能：列使能 *//*參數(shù)說(shuō)明：EnOrDis Enable使能 Disable失能 *//*************************************************************/void ColumEnable(uchar EnOrDis){ if(EnOrDis) { STB=1。 //將串行數(shù)據(jù)傳入輸出鎖存器 STB=0。 //將數(shù)據(jù)鎖存 } else { STB=0。 }}/*************************************************************//*函數(shù)功能：掃描測(cè)試函數(shù) *//*參數(shù)說(shuō)明： *//*************************************************************/void Test(void){ uchar k,j。 RowEnable(Disable)。 //紅全行掃描 for(j=0。j8。j++) { ColumnScan(0xff,0x00,0x00)。 } ColumEnable(Enable)。 for(k=0。k8。k++) { RowScan(k)。 RowEnable(Enable)。 Delay(100)。 RowEnable(Disable)。 } ColumEnable(Disable)。 for(j=0。j8。j++) //綠全行掃描 { ColumnScan(0x00,0xff,0x00)。 } ColumEnable(Enable)。 for(k=0。k8。k++) { RowScan(k)。 RowEnable(Enable)。 Delay(100)。 RowEnable(Disable)。 } ColumEnable(Disable)。 for(j=0。j8。j++) //藍(lán)全行掃描 { ColumnScan(0x00,0x00,0xff)。 } ColumEnable(Enable)。 for(k=0。k8。k++) { RowScan(k)。 RowEnable(Enable)。 Delay(100)。 RowEnable(Disable)。 } ColumEnable(Disable)。 }/****************************************************************************** 功能描述：延時(shí)******************************************************************************/void Delay(uint time){ uint x,y。 for(x=time。x0。x) for(y=100。y0。y)。}附件二：英文資料與中文翻譯英文資料：The Introduction of AT 89C51DescriptionThe AT89C51 is a lowpower, highperformance CMOS 8bit microputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s highdensity nonvolatile memory technology and is patible with the industrystandard MCS51 instruction set and pinout. The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microputer which provides a highlyflexible and costeffective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16bit timer/counters, a five vector twolevel interrupt architecture, a full duplex serial port, onchip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Powerdown Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the loworder address bytes during Flash programming and verification.Port 2Port 2 is an 8bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal pullups. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or