【導(dǎo)讀】本人所呈交的畢業(yè)論文，是在導(dǎo)師的指導(dǎo)下，獨立進行研究所取得的成果。所有數(shù)據(jù)、圖片資料真實可靠。盡我所知，除文中已經(jīng)注明引用的內(nèi)容外，本畢。業(yè)論文的研究成果不包含他人享有著作權(quán)的內(nèi)容。出貢獻的其他個人和集體，均已在文中以明確的方式標明。本論文屬于原創(chuàng)。畢業(yè)論文的知識產(chǎn)權(quán)歸屬于培養(yǎng)單位。指導(dǎo)教師評語（①基礎(chǔ)理論及基本技能的掌握；②獨立解決實際問題的能力；本文研究了如何利用AT89C51單片機控制輸出PWM信號。復(fù)位電路進行了充分的分析。設(shè)計，主要包括電源、顯示、按鍵等外圍電路設(shè)計。出PWM功能，完成了軟件設(shè)計，包括模式選擇、時間選擇、顯示、按鍵程序等。環(huán)Proteus和KeiluVision軟件做了相關(guān)介紹，通過Proteus和KeiluVision. 最終實現(xiàn)了以下功能：能夠通過K1鍵選擇PWM波形的輸出與關(guān)

　　

【正文】 ampus .221, 149 Yanchang Rd, Shanghai 202072, China Introduction PWM technology is a kind of voltage regulation method by controlling the switch frequency of DC power with fixed voltage to modify the twoend voltage of load. This technology can be used for a variety of applications including motor control, temperature control and pressure control and so on. In the motor control system shown as Fig. 1, through adjusting the duty cycle of power switch, the speed of motor can be controlled. As shown in Fig. 2, under the control of PWM signal, the average of voltage that controls the speed of motor changes with Dutycycle D t1/T in this Figure , thus the motor speed can be increased when motor power turn on, decreased when power turn off. : The Relationship between Voltage of Armature and Architecture of PWM Module Therefore, the motor speed can be controlled with regularly adjusting the time of turnon and turnoff. There are three methods could achieve the adjustment of duty cycle: 1 Adjust frequency with fixed pulsewidth. 2 Adjust both frequency and pulsewidth. 3 Adjust pulsewidth with fixed frequency. Generally, there are four methods to generate the PWM signals as the following: 1 Generated by the device posed of separate logic ponents. This method is the original method which now has been discarded. 2 Generated by software. This method need CPU to continuously operate instructions to control I/O pins for generating PWM output signals, so that CPU can not do anything other. Therefore, the method also has been discarded gradually. 3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady work generally has several functions such as overcurrent protection, deadtime adjustment and so on. Then the method has been widely used in many kinds of occasion now. 4 Generated by PWM function module of MCU. Through embedding PWM function module in MCU and initializing the function, PWM pins of MCU can also automatically generate PWM out signals without CPU controlling only when need to change dutycycle. It is the method that will be implemented in this paper. In this paper, we propose a PWM module embedded in a 8051 microcontroller. The PWM module can support PWM pulse signals by initializing the control register and dutycycle register with three methods just mentioned above to adjust the duty cycle and several operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architectures of basic functional blocks. Section3 describes two operation modes. Experimental and simulation results verifying proper system operation are also shown in that section. Depending on mode of operation, the PWM module creates one or more pulsewidth modulated signals, whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in . It is clearly from the diagram that the whole module is posed of two sections: PWM signal generator and deadtime generator with channel select logic. The PWM function can be started by the user through implementing some instructions for initializing the PWM module. In particular, the following power and motion control applications are supported: ? DC Motor ? Uninterruptablel Power Supply UPS ??The PWM module also has the following features: ? Two PWM signal outputs with plementary or independent operation ? Hardware deadtime generators for plementary mode ? Duty cycle updates are configurable to be immediated or synchronized to the PWM Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2output PWM generator shown in is based on a 16bit resolution counter which creates a pulsewidth modulated signal. The system is synthesized by a system clock signal whose frequency can be divided by 4 times or 12 times through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in . To PWM0 generator, the clock to 16bit counter will be predivided by 4 times by default when T3M is set to zero. And the clock will be divided by 12 times when T3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained in detail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCON Channelselect logic The follow Fig. 5 shows the channelselect logic which is useful in Complementary Mode. From this diagram, it is clear to know that signal CP and CPWM control the source of PWMH and PWML. And the details about the two control signals will be discussed in the section 3, and the architecture of deadtime generator will also be discussed in section 5 for the continuity of Complementary Mode. Fig. 5 Diagram of Channelselect Logic Operation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. By setting the corresponding bit CPWM in register PWMCON shown in user can select one of the two operation modes. When CPWM is set to zero, PWM module will work in Independent Mode, whereas, PWM module will work in Complimentary Mode. In the following of this section, the two operation mode will be explained respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which verify the design will also be shown. Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown in Figure 6. A particular PWM output is in the Independent Output mode when the corresponding CP bit in the PWMCON register is set to this case, twochannel PWM outputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0 generator, and the signal on pin PWM1/PWML is from PWM0 generator. The sep