【正文】 abled. The respective topside marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed bytebybyte in either programming mode. To program any nonblank byte in the onchip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.（1）Input the desired memory location on the address lines.（2）Input the appropriate data byte on the data lines.（3）Activate the correct bination of control signals.（4）Raise EA/VPP to 12V for the highvoltage programming mode. （5）Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is selftimed and typically takes no more than ms.（6） Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling:The AT89C51 features Data Polling to indiate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written datum on . Once the write cycle has been pleted, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper bination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming AT89C52 The AT89C52 is a lowpower, highperformance CMOS 8bit microputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s highdensity nonvolatile memory technology and is patible with the industrystandard 80C51 and 80C52 instruction set and pinout The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microputer which provides a highlyflexible and costeffective solution to many embedded control applications.The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16bit timer/counters, a sixvector twolevel interrupt architecture, a fullduplex serial port, onchip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode serial port, and interrupt system to continue functioning. The Powerdown mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Features： Compatible with MCS51? Products 8K Bytes of InSystem Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Threelevel Program Memory Lock256 x 8bit Internal RAM32 Programmable I/O Lines Three 16bit Timer/CountersEight Interrupt Sources Programmable Serial Channel Lowpower Idle and Powerdown ModesPin Description：VCC: Supply voltageGND: Ground附錄B 漢語翻譯中文翻譯AT89系列單片機(jī)摘自《Diste實時信號處理》 AT89C51 特性內(nèi)含4KB的flash存儲器，擦寫次數(shù)1000次；具有可編程的3級程序鎖定器；內(nèi)含128字節(jié)的RAM；具有32根可編程的I/O線；具有2個16位可編程定時器；具有6個中斷源；兩種低功耗工作模式，即空閑模式和掉電模式； 概述AT89C51是一種低功耗，高性能，采用CMOS工藝的8KB的可在線編程的Flash存儲器。該單片機(jī)采用了ATMEL公司的高密度、非易失性存儲器技術(shù)，與工業(yè)標(biāo)準(zhǔn)型MCS51單片機(jī)的指令系統(tǒng)和引腳完全兼容；片內(nèi)的Flash存儲器可在線重新編程，或使用通用的非易失性存儲器編程器；通用的8位CPU與在線可編程Flash集成在一塊芯片上，從而使AT89C51功能更加完善，應(yīng)用更加靈活；具有較高的性能價格比.AT89C51單片機(jī)的封裝形式引腳描述VCC—電源電壓輸入引腳。GND—電源地。P0口—8位、開漏極、雙向I/O口。P0口可用作通用I/O口，但須外接上拉電阻，每個引腳可吸收8個TTL灌電流，當(dāng)作為輸入時，首先應(yīng)將引腳置1。P0口也可用作訪問外部程序存儲器和數(shù)據(jù)存儲器時的低8位地址/數(shù)據(jù)總線的復(fù)用線。在該模式下，P0口含有內(nèi)部上拉電阻。在Flash編程時，P0口接收代碼字節(jié)數(shù)據(jù)；在編程校驗時，P0口輸出代碼字節(jié)數(shù)據(jù)。P1口—8位、雙向I/O口，內(nèi)部含有上拉電阻。P1口可作普通I/O口。輸出緩沖器可驅(qū)動4個TTL負(fù)載；用作輸入時，先將引腳置1，由片內(nèi)上拉電阻將其抬到高電平。P1口的引腳可由外部負(fù)載拉到低電平，通過上拉電阻提供拉電流。在Flash并行編程和校驗時，P1口可輸入地字節(jié)地址。P2口—具有內(nèi)部上拉電阻的8位雙向I/O口。P2口用作輸出口時，可驅(qū)動4個TTL負(fù)載；用做輸入口時，先將引腳置1，由內(nèi)部上拉電阻將其提高到高電平。若負(fù)載為低電平，則通過內(nèi)部上拉電阻向外輸出電流。CPU訪問外部16位地址的存儲器時，在Flash并行編程和校驗時，P2口可輸入高字節(jié)地址和某些控制信號。在P3口—具有內(nèi)部上拉電阻的8位雙向口。P3口用做輸出口時，輸出緩沖器可吸收4個TTL的灌電流；用做輸入口時，首先將引腳置1，由內(nèi)部上拉電阻抬為高電平。若外部的負(fù)載是低電平，則通過內(nèi)部上拉電阻向外輸出電流。在與Flash并行編程和校驗時，P3口可輸入某些控制信號。P3口除了通用I/O功能外，還有替代功能。RST—復(fù)位輸入信號，高電平有效。在振蕩器穩(wěn)定工作時，在RST腳施加兩個機(jī)器周期（即24個晶振周期）以上的高電平，將器件復(fù)位?！獬绦虼鎯ζ髯x選通信號PSEN（Program Store Enable）,低電平有效。當(dāng)AT89C51執(zhí)行來自外部程序存儲器的指令代碼時，每個機(jī)器周期兩次有效。在訪問外部數(shù)據(jù)存儲器時，無效。ALE/—低字節(jié)地址鎖存信號ALE（Address Latch Enable）。在系統(tǒng)擴(kuò)展時，ALE的下降沿將P0口輸出的低8位地址瑣存在外接的地址瑣存器中，以實現(xiàn)低字節(jié)地址和數(shù)據(jù)的分時傳送。此外，ALE端連續(xù)輸出正脈沖，頻率為晶振頻率的1/6，可用做外部定時脈沖使用。但要注意，每次訪問外RAM時要丟失一個ALE脈沖。再編程期間，該引腳輸入編程脈沖（）。如果需要，則通過SFR（8EH）的第0位置1，可禁止ALE操作，但在使用MOVC或MOVX指令時，ALE仍然有效。也就是說，ALE的禁止位不影響對外部存儲器的訪問。/Vpp—外部程序存儲器訪問允許信號EA（External Access Enable）。當(dāng)信號接地時，CPU只執(zhí)行片外程序存儲器中的程序；當(dāng)接Vcc時，CPU首先執(zhí)行片內(nèi)程序存儲器中的程序（0000H0FFFH），然后自動