【導讀】各種情況下都涉及到相同的主要操作：信息的處理、信息的存儲和信息的傳遞。子計數(shù)器還是機械計數(shù)器，都要存儲當前的數(shù)值，并且按要求將該數(shù)值增加1。系統(tǒng)例如采用計數(shù)器的電子鐘之類的任一系統(tǒng)要使其存儲和處理能力遍布整個系統(tǒng)，處理，信息的存儲和信息的傳輸三個功能分離形成不同的系統(tǒng)單元。針對微計算機的設(shè)想。從此以后基本上所有制成的計算機都是用這種結(jié)構(gòu)設(shè)計的，盡。在以微處理器為基礎(chǔ)的系統(tǒng)中，處理是由以微處理器為基礎(chǔ)的系統(tǒng)自身完成的。要在一個以微處理器為基礎(chǔ)的時鐘中找出執(zhí)行具有計數(shù)功能的一個。由于系統(tǒng)幾乎完全由軟件所定義，所以對微處理器結(jié)構(gòu)和其輔助電。該系統(tǒng)由微處理器控制，微處理器能夠?qū)ζ渥?。用電察除，所以稱為電可察除可編程只讀存儲器EEPROM。計算機，結(jié)果使最終產(chǎn)品的裝配成本得以節(jié)省。壓力變送器實現(xiàn)壓力測量并產(chǎn)生正比于所傳感壓力的氣動或電信號輸出。了消除這一問題，開發(fā)了一種信號傳輸系統(tǒng)。

　　

【正文】 circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Powerdown Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC： Supply voltage. GND： Ground. Port 0： Port 0 is an 8bit opendrain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification. Port 1 Port 1 is an 8bit bidirectional I/O port with internal Port 1 output buffers can sink/source four TTL 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal 1 also receives the loworder address bytes during Flash programming and verification. Port 2 Port 2 is an 8bit bidirectional I/O port with internal Port 2 output buffers can sink/source four TTL 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8bit addresses, Port 2 emits the contents of the P2 Special Function 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8bit bidirectional I/O port with internal Port 3 output buffers can sink/source four TTL 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on should be strapped to VCC for internal program pin also receives the 12volt programming enable voltage(VPP) during Flash programming, for parts that require12volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop, but minimum and maximum voltage high and low time specifications must be observed.