【文章內(nèi)容簡介】 erves the functions of various special features of the AT89S51 as shown in the following table Port Pin Alternate Functions P30 RXD serial input port P31 TXD serial output port P32 INT0 external interrupt 0 P33 INT1 external interrupt 1 P34 T0 timer 0 external input P35 T1 timer 1 external input P36 WR external data memory write strobe P37 RD external data memory read strobe 3 Memory Organization MCS51 devices have a separate address space for Program and Data Memory Up to 64K bytes each of external Program and Data Memory can be addressed 31 Program Memory If the EA pin is connected to GND all program fetches are directed to external memory On the AT89S51 if EA is connected to VCC program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory 32 Data Memory The AT89S51 implements 128 bytes of onchip RAM The 128 bytes are accessible via direct and indirect addressing modes Stack operations are examples of indirect addressing so the 128 bytes of data RAM are available as stack space 4 Watchdog Timer Onetime Enabled with Resetout The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets The WDT consists of a 14bit counter and the Watchdog Timer Reset WDTRST SFR The WDT is defaulted to disable from exiting reset To enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled it will increment every machine cycle while the oscillator is running The WDT timeout period is dependent on the external clock frequency There is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT overflows it will drive an output RESET HIGH pulse at the RST pin 41 Using the WDT To enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow The 14bit counter overflows when it reaches 16383 3FFFH and this will reset the device When the WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must reset the WDT at least every 16383 machine cycles To reset the WDT the user must write 01EH and 0E1H to WDTRST WDTRST is a writeonly register The WDT counter cannot be read or written When WDT overflows it will generate an output RESET pulse at the RST pin The RESET pulse duration is 98xTOSC where TOSC 1FOSC To make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset 42 WDT DURING Powerdown and Idle In Powerdown mode the oscillator stops which means the WDT also stops While in Powerdown mode the user does not need to service the WDT There are two methods of exiting Powerdown mode by a hardware reset or via a levelactivated external interrupt which is enabled prior to entering Powerdown mode When Powerdown is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89S51 is reset Exiting Powerdown with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Powerdown mode To ensure that the WDT does not overflow within a few states of exiting Powerdown it is best to reset the WDT just before entering Powerdown mode Before going into the IDLE mode the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled The WDT keeps counting during IDLE WDIDLE bit 0 as the default state To prevent the WDT from resetting the AT89S51 while in IDLE mode the user should always set up a timer that will periodically exit IDLE service the WDT and reenter IDLE mode With WDIDLE bit enabled the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE 5Interrupts The AT89S51 has a total of five interrupt vectors two external interrupts INT0 and INT1 two timer interrupts Timers 0 and 1 and the serial port interrupt These interrupts are all shown in Figure 61 Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE IE also contains a global disable bit EA which disables all interrupts at once 6 Oscillator Characteristics XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier that can be configured for use as an onchip oscillator as shown in Figure 71 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 72 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a dividebytwo flipflop but minimum and imum voltage high and low time specifications must be observed 7 Idle Mode In idle mode the CPU puts itself to sleep while all the onchip peripherals remain active The mode is invoked by software The content of the onchip RAM and all the special function registers remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset Note that when idle mode is terminated by a hardware reset the device normally resumes program execution from where it left off up to two machine cycl