i2c總線協(xié)議簡介畢業(yè)論文外文文獻翻譯(編輯修改稿)
2025-09-06 07:36 本頁面
【文章內(nèi)容簡介】 the transmission of a byte. In this case, no acknowledge is generated. ARBITRATION AND CLOCK GENERATION、 SynchronizationAll masters generate their own clock on the SCL line to transfer messages on the I2Cbus. Data is only valid during the HIGH period of the clock. A defined lock is therefore needed for the bitbybit arbitration procedure to take place.Clock synchronization is performed using the wiredAND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached. However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH waitstate during this time.When all devices concerned have counted off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to plete its HIGH period will again pull the SCL line LOW.In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. 、 ArbitrationA master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (tHD。STA) of the START condition which results in a defined START condition to the bus.Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level.Arbitration can continue for many bits. Its first stage is parison of the address bits (addressing information is given in Sections 10 and 14). If the masters are each trying to address the same device, arbitration continues with parison of the databits if they are mastertransmitter,or acknowledgebits if they are masterreceiver. Because address and data information on the I2Cbus is determined by the winning master, no information is lost during the arbitration process.A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration.As an Hsmode master has a unique 8bit master code, it will always finish the arbitration during the first byteIf a master also incorporates a slave function and it loses arbitration during the addressing stage, it’s possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode.Figure 9 shows the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to
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