【文章內(nèi)容簡(jiǎn)介】 nter enable*/ TIM2CR1|=0x0001。 //開TIM2 /*Trigger and Update interrupt enabled*/ TIM2DIER|=0x0041。 //開TIM2中斷 }void huan_xiang(){ step = GPIO_ReadInputData(GPIOA)amp。0x0007。 if(direction_flag==MotorForwardFlag) { switch(step)//根據(jù)轉(zhuǎn)子位置，決定CCER輸出相位和轉(zhuǎn)子偏移量 { case 0x06: { /*0011 0100 0010 0000 reset CC3NP CC3P CC3E CC2NP CC2NE CC2E CC1NP CC1NE CC1P CC1E set CC2P OC2 active low,set CC3NE OC3N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS3, OIS3N and CC3E bits set CC4P OC4 active low,set CC4E OC4 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1CCER =0x3420。// }。 break。 case 0x04: { /*0011 0000 0010 0100 set CC2P OC2 active low,set CC1NE OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1CCER =0x3024。// }。 break。 case 0x05: { /*0011 0010 0000 0100 set CC3P OC3 active low,set CC1NE OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1CCER =0x3204。// }。 break。 case 0x01: { /*0011 0010 0100 0000 set CC3P OC3 active low,set CC2NE OC2N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS2, OIS2N and CC2E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1CCER =0x3240。// }。 break。 case 0x03: { /*0011 0000 0100 0010 set CC1P OC3 active low,set CC2NE OC2N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS2, OIS2N and CC2E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1CCER =0x3042。// }。 break。 case 0x02: { /*0011 0100 0000 0010 set CC1P OC1 active low,set CC3NE OC3N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS3, OIS3N and CC3E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1CCER =0x3402。// }。 break。 } } else//倒轉(zhuǎn) { switch(step) { // case 0x06: { TIM1CCER =0x3420。 // 3?2 }。 break。 case 0x04: { TIM1CCER =0x3024。 // 3?6 }。 break。 case 0x05: { TIM1CCER =0x3204。 // 1?6 }。 break。 case 0x01: { TIM1CCER =0x3240。 // 1?4 }。 break。 case 0x03: { TIM1CCER =0x3042。 }。 break。 case 0x02: { TIM1CCER =0x3402。 }。 break。 default: { TIM1CCER =0x0000。 } break。 } }}//定時(shí)器2采集霍爾信號(hào)，產(chǎn)生六步換向的觸發(fā)中斷條件void TIM2_Configuration(void){ TIM_TimeBaseInitTypeDef TIM_HALLTimeBaseInitStructure。 TIM_ICInitTypeDef TIM_HALLICInitStructure。 TIM_OCInitTypeDef TIM_HALLOCInitStructure。 /*Deinitializes the TIM2 peripheral registers to their default reset values */ TIM_DeInit(TIM2)。 /*Fills each TIM_TimeBaseInitStruct member with its default value Set the default configuration TIM_TimeBaseInitStructTIM_Period = 0xFFFF。 TIM_TimeBaseInitStructTIM_Prescaler = 0x0000。 TIM_TimeBaseInitStructTIM_ClockDivision = TIM_CKD_DIV1。 TIM_TimeBaseInitStructTIM_CounterMode = TIM_CounterMode_Up。 TIM_TimeBaseInitStructTIM_RepetitionCounter = 0x0000。 */ TIM_TimeBaseStructInit(amp。TIM_HALLTimeBaseInitStructure)。 // Set full 16bit working range = 65535。//TIM2_ARR=65535 //PSC預(yù)分頻 計(jì)數(shù)器的時(shí)鐘頻率CK_CNT=fck_psc/(psc[15:0]+1) 1MHz = 71。//1us計(jì)數(shù)1 = TIM_CounterMode_Up。//CR1 向上計(jì)數(shù) = TIM_CKD_DIV1。//CR1 定時(shí)器時(shí)鐘頻率和數(shù)字濾波器使用的采樣頻率之間的分頻比例 /*每次從零開始計(jì)數(shù)時(shí)，產(chǎn)生更新事件（UEV）*/ = 0。//RCR TIM_TimeBaseInit(TIM2,amp。TIM_HALLTimeBaseInitStructure)。 /*Fills each TIM_ICInitStruct member with its default value Set the default configuration TIM_ICInitStructTIM_Channel = TIM_Channel_1。 TIM_ICInitStructTIM_ICPolarity = TIM_ICPolarity_Rising。 TIM_ICInitStructTIM_ICSelection = TIM_ICSelection_DirectTI。 TIM_ICInitStructTIM_ICPrescaler = TIM_ICPSC_DIV1。 TIM_ICInitStructTIM_ICFilter = 0x00。 */ TIM_ICStructInit(amp。TIM_HALLICInitStructure)。 //。 //CCER 0x0000 1通道禁止捕獲 ？？？ = TIM_Channel_1。 //CCER 0x0000 輸入捕獲上升沿時(shí)，通道1不反向。 /*reset the CC1P This bit selects IC1 is used for capture operations. capture is done on a rising edge of IC1. */ = TIM_ICPolarity_Rising。 //CCMR1 輸入通道與TRC相連 /* CC1S[1:0] 11 CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) */ = TIM_ICSelection_TRC。 //每捕獲到一個(gè)邊沿執(zhí)行一次 /*定時(shí)器時(shí)鐘頻率和數(shù)字濾波器使用的采樣頻率之間的分頻比例為1*/ = TIM_ICPSC_DIV1。 //CCMR1 輸入比較濾波器 = 0x09。 TIM_ICInit(TIM2,amp。TIM_HALLICInitStructure)。 /*Fills each TIM_OCInitStruct member with its default value Set the default configuration TIM_OCInitStructTIM_OCMode = TIM_OCMode_Timing。 TIM_OCInitStructTIM_OutputState = TIM_OutputState_Disable。 TIM_OCInitStructTIM_OutputNState = TIM_OutputNState_Disable。 TIM_OCInitStructTIM_Pulse = 0x0000。 TIM_OCInitStructTIM_OCPolarity = TIM_OCPolarity_High。 TIM_OCInitStructTIM_OCNPolarity = TIM_OCPolari