【文章內(nèi)容簡介】 of treatment by the microprocessor, in a variety of different applications in different circuits, in general, the data may be processed so have several situations: 1 ? address (such as MOV DPTR, 1000H), that address 1000h into the DPTR. 2 ? the way the words or control characters (such as MOV TMOD, 3), 3 which controls the characters. 3 ? constants (such as MOV TH0, 10H) 10H that is constant from time to time. 4 ? The actual output value (such as the mouth then P1 lantern light to light the whole, then the implementation of instruction: MOV P1, 0FFH, to light the whole dark, then the implementation of instruction: MOV P1, 00H) and 00H are here 0FFH actual output value. Another example is the font code for the LED, is the actual output value. Understanding of the address, the nature of instructions, running is not difficult to understand why the process of running fly, the data will be implemented as instructions. Three, P0 mouth, P2 and P3 the mouth of the second function Usage: often on P0 beginner I, P2 and P3 mouth I use the second function puzzled think the second function and the original features have a switch between the process, or that there have to be a directive, in fact, the port39。s second feature is pletely automatic, no need to use mand to convert. Such as , , respectively, are WR, RD signal, when the microchip RAM or external justifications machine has an external I / O port, they were used as the second function, can not be used as generalpurpose I / O port to use, as long as one microprocessor implementation of the MOVX instruction 1, there will be a corresponding signal sent from the or , no prior use instructions indicate. In fact 39。can not be used as generalpurpose I / O port use39。 is not 39。should not39。 but (user) 39。not39。 as a generalpurpose I / O port to use. At mand you can arrange a Medium of Instruction SETB , and when the singlechip implementation of this Article directions, will also bee high, but users will not do so, because This usually will lead to the collapse of the system. Four, the program implementation process: singlechip poweron reset in 8051 after the program counter (PC) in the value of39。0000 39。, so the procedure always39。000039。 unit begin implementation of, that is to say: the system39。s ROM must exist in the39。0000 39。in this unit, and39。000039。 in the storage unit must be a mand. Friday, the stack: the stack is a region, are used to store data, the region does not have any unique position, that is a part of internal RAM, special is its data storage and access methods, namely, the socalled 39。advanced after that lastin firstout 39。, and the stack has a special data transmission mand, ie39。 PUSH 39。and39。 POP 39。, there is a special unit specifically for its services, that is, the stack pointer SP, when they first PUSH instruction, the SP on (at the original value of the foundation on) automatically add one, whenever the implementation of a POP instruction, SP on (at the original value basis) minus one automatically. Because of the value of SP can be used to change directions, so as long as the stage at the beginning of the proceedings to change the value of the SP, you can put the stack set up the required memory units, such as at the beginning of the proceedings, with a MOV SP, 5FH instructions when put on the stack from the memory modules installed in the unit 60H start. The normal procedure at the beginning of the total that there is a stack pointer of the instruction set, because at startup, SP initial value of 07H, thus the stack from the beginning the next unit 08h, and 08h to 1Fh in the region 8031 is the second, Three, four working registers area, often used, this will lead to data chaos. The author has prepared a different program, not exactly the same instructions to initialize the stack, which is the author39。s customary problem. When set up the stack area, does not mean that the region as a dedicated memory, it can be as mon as the use of memory region, but under normal circumstances programming will not put it as an ordinary memory use. AVR single chip The AVR core bines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features: 8K bytes of InSystem Programmable Flash with ReadWhileWrite capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with pare modes, internal and external interrupts, a serial program mable USART, a byte oriented Twowire Serial Interface, a 6channel ADC (eight channels in TQFP and MLF packages) where four (six) channels have 10bit accuracy and two channels have 8bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hard ware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys tal/resonator Oscillator is running while