【文章內容簡介】 , including microprocessors, memories, main boards and other structural ponents. On the lower level, the system’s behavior is described by Bolivia equations. For their execution, logical elements and triggers are used. 4. USE OF VHDL FOR SYNTHESIS OF STRUCTURAL AND BEHAVIORAL MODELS VHDL is a Hardware Description Language for describing digital system [2]. VHDL is designed to full a number of needs in the design process. VHDL contains a number of facilities for modifying the state of objects and controlling the flow of execution of modules. In VHDL, an entity is such a module which may be used as a ponent in a design, or which may be the toplevel module of the design. The entity declarative part may be used to declare items, which are to be used in the implementation of the entity. Once an entity has had its interface specified in an entity declaration, one or more implementations of the entity can be described in architecture bodies. Each architecture body can describe a different view of the entity. The declarations in the architecture body define items that will be used to construct the design description. Signals are used to connect sub modules in a design. The sub modules in an architecture body can be described as blocks. A block is a unit of module structure, with its own interface, connected to other blocks or ports by signals. A signal assignment schedules one or more transactions to a signal (or port). The primary unit of behavioral description in VHDL is the process. When more than one process is activated at the same time, they execute concurrently. A process statement which can be used in an architecture body or block. The declarations define items which can be used locally within the process. A process may contain a number of signal assignment statements for a given signal, which together form a driver for the signal. VHDL descriptions write them in a design file. After then invoke a piler to analyze them and insert them into a design library. A number of VHDL constructs may be separately analyzed for inclusion in a design library. These constructs are called library units. A design file may contain a number of library units. The behavioral model represents a functional interpretation of the designed digital system. The hardware of the digital device is regarded as a kind of a discreet system. Its behavior is described as a number of operations. These operations are applied within the system’s database. Within the creation of behavioral VHDL models, operations are described by processes and their interconnectionsby signals. On fig 1 is presented a VHDL model of a linear decipherer. library IEEE。 use 。 entity DESHIF is port (x1,x2,x3 in: std_logic。 J: out std_logic_vector(0 to 7))。 end DESHIF。 arhitecture STRUCTURAL of DESHIF is ponent AND3 port (I1,I2,I3: in std_logic。 O1: out std_logic)。 end ponent。 ponent NOT1 port (I1: in std_logic。 O1: out std_logic)。 end ponent。 signal a,b,c: std_logic。 begin U1: NOT1 port map (I1=x1,O1=a)。 U2: NOT1 port map (I1=x2,O1=b)。 U3: NOT1 port map (I1=x3,O1=c)。 U4: AND3 port map (I1=a,I2=b,I3=c,O1=J(0))。 U5: AND3 port map (I1=a,I2=b,I3=x3,O1=J(1))。 U6: AND3 port map (I1=a,I2=x2,I3=c,O1=J(2))。 U7: AND3 port map (I1=a,I2=x2,I3=x3,O1=J(3))。 U8: AND3 port map (I1=x1,I2=b,I3=c,O1=J(4))。 U9: AND3 port map (I1=x1,I2=b,I3=x3,O1=J(5))。 U10: AND3 port map (I1=x1,I2=x2,I3=c,O1=J(6))。 U11: AND3 port map (I1=x1,I2=x2,I3=x3,O1=J(7))。 end STRUCTURAL。 architecture DATA_FLOW of DESHIF is signal T1,T2,T3: bit。 begin T1= not x1。 T2= not x2。 T3= not x3。 F1=T1 and T2 and T3。 F2=T1 and T2 and x3。 F3=T1 and x2 and T3。 F4=T1 and x2 and x3。 F5=x1 and T2 and T3。 F6=x1 and T2 and x3。 F1=x1 and x2 and T3。 F1=x1 and x2 and x3。 end DATA_FLOW。 VHDL code of a linear decipherer Structural VHDL models are means for reflecting the project’s hierarchy. They are built up by deposition of digital systems of functionally interconnected parts. These parts are presented as ponents, and their interconnections are realized through signals. These signals enter and exit the ponents via ports. For example, within the designing of the digital module, presented on [2], its structural model has three main ponentscounter, decoder and lightdiode sevensegment display. On is shown