電子萬年歷外文翻譯-其他專業(yè)(編輯修改稿)
2025-02-24 03:21 本頁面
【文章內(nèi)容簡介】 nd LED displays for all the test mode (5) can drive8LED display (6) the internal RAM address 01~ 08H respectively corresponding to DIG0 ～DIG7. (7) scan register ( address:0BH ) the register in the D0 ~ D3 bits of data of the set value is 0 ～ 7H, set the value of said display dynamic scanning digital from 1 to8. (8) stop register ( address:0CH ) when D0=0, MAX721is in a halt state。 when D0=1, in a normal working state. (9) showed the test register ( address:0FH ) when D0=0, MAX7219according to a set pattern in normal work。 when D0=1, in beta status. In this state, regardless of the MAX7219in what mode, all of the LED will be the maximum brightness display. (10) the brightness register ( address:0AH ) luminance can use the hardware and software of the two methods to regulate brightness registers in the D0 ～ D3can control LED display. LED display register by an internal8x 8static RAM, the operator can direct positioning of individually addressable register, to refresh and keep the data, as long as more than 2 V ( V + for + 5V ). *********************** 5 Control register includes: decoding mode, display brightness adjustment, scan limits ( select scan digits), shutdown and display the test register. 6 DS1302working mode and data operation principle DS1302can be years, months, days, weeks, when, minutes and seconds for time, and has a leap year pensation function, wide voltage up to ~. Using a three wire interface synchronization with CPU munication, and may use a burst mode a transmission of multiple byte clock signal or RAM data. DS1302has a33x8for temporary storage of data RAM register. DS1302 is a DS1202 upgrade products, patible with DS1202, but the increase of main power supply dual power supply pins / back to back, while providing a power supply current trickle charging capability. DS1302 clock chip includes a real time clock / calendar and31 bytes of static RAM. It passes through a simple serial interface and munication. Real time clock / calendar with seconds, hours, days, weeks, months and years of information. For less than 31days at the end of the month and the date is automatically adjusted, also includes a leap year correction function. The operation of the clock can be used with AM/PM24 or12 hour format. Using a three wire interface synchronization with CPU munication, and may use a burst mode a transmitted byte clock signal or RAM data. DS1302 in any transmission of data must be initialized, the RST foot placement is high, then the8 bits of the address and mand words into the shift register, the data at the rising edge of SCLK was access to. At the beginning of the 8clock cycle, the mand byte loaded into the shift register, another clock cycle during a read operation when the output data, in a write operation for writing data. The number of clock pulses in single byte mode for8+8, in multiple byte mode for8+ bytes, the maximum is 248bytes. If the transmission of the midmounted RST feet for low level, it will terminate the data transmission, and the I/O pin into a high resistance state. *********************** 6 Power on run time, the Vcc ≥, RST foot must be kept low level. Only when the SCLK is low, can be set to hi
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鄂ICP備17016276號-1