【正文】 區(qū)包圍有源區(qū) d 5 n+、 p+保護(hù)環(huán) ~有源區(qū) e 10 n+、 p+保護(hù)環(huán)寬度 f 5 nmos、 pmos多晶硅柵寬度 g 6 多晶硅柵伸出有源區(qū) h 12 多晶硅柵與 n+、 p+保護(hù)環(huán)迭搭 i 2 多晶硅柵 ~鋁布線 j 1 p阱包圍 p+保護(hù)環(huán) k 2 ………….. 2022/2/4 Jian Fang 68 DRC文件例子 (片斷 ) (drc metal (width ) ) (drc metal (sep ) ) (drc metal omicont (enc ) ) (drc poly omicont (enc ) ) 2022/2/4 Jian Fang 69 EXTRACT 用圖層間的相對(duì)關(guān)系判定器件及相互連接關(guān)系 . 例如 : Poly跨過(guò) Active,即同時(shí)出現(xiàn) Poly和Active表明有一個(gè)MOS器件 . Extracts electrical circuit: transistors, connections, capacitance, resistance IN Out Vdd Gnd 2022/2/4 Jian Fang 70 EXTRACT文件例子 (片斷 ) (extractDevice ngate (poly G) (nsd S D) (pwell1 B) nmos4 symbol analogLib ) (extractDevice pgate (poly G) (psd S D) (sub B) pmos4 symbol analogLib ) pgateWidth=measureParameter(length (pgate coincident poly) ) pgateLength=measureParameter(length (pgate inside poly) ) saveParameter(pgateWidth W) saveParameter(pgateLength L) ngateWidth=measureParameter(length (ngate coincident poly) ) ngateLength=measureParameter(length (ngate inside poly) ) saveParameter(ngateWidth W) saveParameter(ngateLength L) 2022/2/4 Jian Fang 71 LVS 10 10 10 10 10 10 40 EXT LVS Layout versus schematic transistors: parallel or serial Compares electrical circuits: (schematic and extracted layout) 2022/2/4 Jian Fang 72 ERC Electrical rule check Checks electrical circuit: unconnected inputs shorted outputs correct power and ground connection 2022/2/4 Jian Fang 73 Digital design ? Behavioral simulation ? ……………….. ? Simulation/timing verification with estimated backannotation ? Place and route (place and route rules) ? Design Rule Check, DRC (DRC rules) ? Loading extraction (rules and parameters) ? Simulation/timing verification with real backannotation ? Design export ? ……………………….. 2022/2/4 Jian Fang 74 Place and Route ? Generates final chip from gate level list ? Goals: Minimum chip size Maximum chip speed. ? Placement: ? Placing all gates to minimize distance between connected gates ? Floor planning tool using design hierarchy ? Specialized algorithms ( min cut, simulated annealing, etc.) ? Timing driven ? Manual intervention ? Very pute intensive Hierarchy based floor planning Simulated annealing High temperature: move gates randomly Low temperature: Move gates locally Min cut Keep cutting design into equal sized pieces For each cut: Move gates around until minimum connection across cut 2022/2/4 Jian Fang 75 ? Routing: ? Channel based: Routing only in channels between gates (few metal layers: 2) ? Channel less: Rou