【正文】 J62接到 RS232amp。結(jié)果可按左對(duì)齊或右對(duì)齊的方式存放在 16位寄存器中。 如果是 單次 模式，啟動(dòng)后一次轉(zhuǎn)換完成后不再轉(zhuǎn)換，如果是 連續(xù) 模式，則一次轉(zhuǎn)換完后繼續(xù)反復(fù)轉(zhuǎn)換。 = ADC_ExternalTrigConv_None。 ? void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)。 ? void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)。 ? void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)。 ? void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)。 ? FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)。 /* Enable ADC1 */ ADC_Cmd(ADC1, ENABLE)。 6 STM32的 A/D轉(zhuǎn)換器 ? ADC端口： PA0~PA7:ADC_IN0~ADC_IN7 PB0~PB1:ADC_IN8~ADC_IN9 PC0~PC5:ADC_IN10~ADC_IN15 ? 輸入信號(hào)量程： VREF~VREF+(0~) ? 本電路板的模擬電壓（電位器）連在 PC0端口。 ? ADC 輸入范圍 : VREF ≤ VIN ≤ VREF+ (VREF+ and VREF available only in LQFP100 package) ? 精度： 12位。 STM32的 16個(gè)外部 ADC通道可分為兩組 :規(guī)則的和注入的。 = ADC_DataAlign_Right。 ? void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)。 ? void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)。 *函數(shù)說明參考 課本 附錄 C表 ， p335頁(yè) 18 STM32的 ADC介紹 ? ADC 轉(zhuǎn)換率達(dá) 1 MHz，精度為 12位 ? ADC 電源要求 : to V ? ADC 輸入范圍 : VREF ≤ VIN ≤ VREF+ (VREF+ and VREF available only in LQFP100 package) ? Dual mode (on devices with 2 ADCs): 8 conversion mode ? 多達(dá) 18個(gè)通道 : ? 16 external channels ? 2 internal channels: 與溫度傳感器和內(nèi)部參考電壓連接 (Bandgap voltage) ? Channels conversion groups: ? Up to 16 channels regular group ? Up to 4 channels injected group ? Single and continuous conversion modes 19 STM32的 ADC介紹 ? 自動(dòng)從通道 0 到通道 ‘n’ 進(jìn)行轉(zhuǎn)換的掃描模式 ? Channel by channel programmable sampling time and conversion order ? Discontinuous mode on regular and injected groups ? Selfcalibration ? Left or right Data alignment with inbuilt data coherency ? Analog Watchdog on high and low thresholds ? Interrupt generation on: ? End of Conversion ? End of Injected conversion ? Analog watchdog ? DMA capability (only on ADC1) 20 ADC Block Diagram TIM1_CC1 TIM1_CC2 TIM1_CC3 TIM2_CC2 TIM3_TRGO TIM4_CC4 TIM1_TRGO TIM1_CC4 TIM1_TRGO TIM2_CC1 TIM3_CC4 TIM4_TRGO ANALOG MUX GPIO Ports Temp Sensor VREFINT ADC Up to 4 Up to 16 Injected Channels Regular Channels JEXTRIG bit Start Trigger (injected group) VREF+ VREF VDDA VSSA ADC_IN0 ADC_IN1 ADC_IN15 . . . Ext_IT_15 Ext_IT_11 EXTRIG bit Start Trigger (regular group) JEXTSEL[2:0] bits EXTSEL[2:0] bits Injected data registers (4x12bits) Address/data bus Regular data register (12bits) DMA Request ADCCLK ADC Prescalers: Div2, Div4, Div6 and Div8 PCLK2 Analog Watchdog High Threshold register (12bits) Low Threshold register (12bits) AWD EOC JEOC AWDIE EOCIE JEOCIE Flags Interrupt enable bits Analog watchdog event End of injected conversion End of conversion ADC interrupt to NVIC 21 ADC Regular channels group ? Programmable number of regular channels: Up to 16 channels ? Programmable sample time and order of each channel in the conversion sequence ? Conversion started by: ? Software through start bit ? External trigger generated by: ? Timer1 CC1 ? Timer1 CC2 ? Timer1 CC3 ? Timer2 CC2 ? Timer3 TRGO ? Timer4 CC4 ? EXTI Line11 22 ADC Injected channels group ? Programmable number of injected channels: Up to 4 channels ? Programmable sample time and order of each channel in the conversion sequence ? Conversion started by: ? JAUTO: automatic injected conversion after regular channels conversion ? Software through start bit ? External trigger generated by: ? Timer1 TRGO ? Timer1 CC4 ? Timer2 TRGO ? Timer2 CC1 ? Timer3 CC4 ? Timer4 TRGO ? EXTI Line15 23 Analog sample time ? ADCCLK, up to 14MHz, taken from PCLK2 through a prescaler (Div2, Div4, Div6 and Div8) ? Three bits programmable sample time cycles for each channel: ? cycles ? cycles ? cycles ? cycles ? cycles ? cycles ? cycles ? cycles ? Total conve