【正文】 s this is a mon FPGA logic element. VPACK is also capable of targeting logic blocks that contain several LUTs and several flip flops， with or without shared LUT inputs [6]. These “clusterbased”logic blocks are similar to those employed in recent FPGAs by Altera， Xilinx and Lucent Technologies. 2 Placement Algorithm VPR uses the simulated annealing algorithm [7] for placement. We have experimented with several different cost functions， and found that what we call a linear congestion cost function provides the best results in a reasonable putation time [8].The functional form of this cost function is where the summation is over all the s in the circuit. For each ， bbx and bby denote the horizontal and vertical spans of its bounding box， respectively. The q(n)factor pensates for the fact that the bounding box wire length model underestimates the wiring necessary to connect s with more than three terminals， as suggested in [10]. 14 Its value depends on the number of terminals of n。在世嘉列中的條目 179。 VPR要求比第二，第三最 佳路由器降低 10％的資源數(shù)目，表 3列出了音軌需要執(zhí)行這些標(biāo)準(zhǔn)時(shí)數(shù)新的 CAD工具，同時(shí)允許地方和路線的電路的連接。圖 3說明了差異圖形。通過逐漸增加的多余認(rèn)購路由資源成本，該算法勢力替代路線網(wǎng)，以避免使用超額認(rèn)購資源，只剩下網(wǎng)最需要一個(gè)給定的資源。當(dāng)溫度是如此之高，幾乎任何舉動(dòng)都可以被接受時(shí)，我們基本上從一個(gè)位置隨機(jī)移動(dòng)到另一個(gè)位置所改善獲得的成本都是小成本。邊界線長度模型中的實(shí)際低估所需的布線，就可以看成超過三個(gè)終端網(wǎng)，作為建議 [10]。最后，如 果合并后的全球和詳細(xì)的路由被執(zhí)行，一個(gè)也會(huì)進(jìn)行求值： ?開關(guān)塊 [1]架構(gòu)（即為何路由曲目是相互關(guān)聯(lián)的）， ?曲目號(hào)碼，每個(gè)邏輯塊的輸入引腳連接（ [1]）， ?為邏輯塊輸出 FC值， ?對 I / O口 FC值。也就是說評估基準(zhǔn)電路技術(shù)映射，放置和 FPGA的布線結(jié)構(gòu)上的關(guān)系和措施的架構(gòu)質(zhì)量，如運(yùn)算速度或區(qū)域，然后可以很容易地提取出來。因此，有相當(dāng)大的對于靈活 CAD工具的 需求，這樣才可以針對各種架構(gòu)的 FPGA 做高效的設(shè)計(jì)，從而便于比較均勻的設(shè)計(jì)架構(gòu)。 3 當(dāng)前的體系結(jié)構(gòu)描述格式不允許跨越多個(gè)領(lǐng)域和多個(gè)邏輯塊和被列入路由體系結(jié)構(gòu)，但我們目前加入此功能。它的價(jià)值取決于凈 N兩端號(hào)碼 。相反，如果動(dòng)作是很少被接受（ 因溫度當(dāng)前正處于低位，安置相當(dāng)高的品質(zhì)），也有不少改善成本。對于本文的實(shí)驗(yàn)結(jié)果，我們設(shè)置路由器的最大數(shù)量迭代為 45，如果電路中路由沒有成功，一定數(shù)目的目錄中 45迭代就被假定為不可路由通道的寬度。 5實(shí)驗(yàn)結(jié)果 各種 FPGA在本節(jié)中使用的參數(shù)，總是選擇與先前參數(shù)有明顯對比的那些參數(shù)。列出所有電路邏輯快的消息清單。仿真無法成功，因?yàn)槭兰芜\(yùn)行路由內(nèi)存不足。 q is 1 for s with 3 or fewer terminals， and slowly increases to for s with 50 ， x(n) and Cav， y(n) are the average channel capacities (in tracks) in the x and y directions， respectively， over the bounding box of cost function penalizes placements which require more routing in areas of the FPGA that have narrower channels. All the results in this paper， however， are obtained with FPGAs in which all channels have the same capacity. In this case Cav is a constant and the linear congestion cost function reduces to a bounding box cost good annealing schedule is essential to obtain highquality solutions in a reasonable putation time with simulated annealing. We have developed a new annealing schedule which leads to very highquality placements， and in which the annealing parameters automatically adjust to different cost functions and circuit sizes. We pute the initial temperature in a manner similar to [11]. Let Nblocks be the total number of logic blocks plus the number of I/O pads in a circuit. We first create a random placement of the circuit. Next we perform Nblocks moves (pairwise swaps) of logic blocks or I/O pads， and pute the standard deviation of the cost of these Nblocks different configurations. The initial temperature is set to 20 times this standard deviation， ensuring that initially virtually any move is accepted at the start of the in [12]， the default number of moves evaluated at each temperature is. This default number can be overridden on the mand line， however， to allow different CPU time / placement quality tradeoffs. Reducing the number of moves per temperature by a factor of 10， for example， speeds up placement by a factor of 10 and reduces final placement quality by only about 10%.When the temperature is so high that almost any move is accepted， we are essentially moving randomly from one placement to another and little improvement in cost is obtained. Conversely， if very few moves are being accepted (due to the temperature being low and the current placement being of fairly high quality)， there is also little improvement in cost. With this motivation in mind， we propose a new temperature update schedule which increases the amount of time spent at temperatures where a significant fraction of， but not all， moves are being accepted. A new temperature is puted as Tnew = a Told， where the value of a depends on the fraction of attempted moves that were accepted (Raccept) at Told， as shown in Table ， it was shown in [12， 13] that it is desirable to keep 15 Raccept near for aslong as possible. We acplish this by using the value of Raccept to control a range limiter only interchanges of blocks that are less than or equal to Dlimit units apart in the x and y directions are attempted. A small value of Dlimit increases Raccept by ensuring that only blocks which are close together are considered for swapping. These“l(fā)ocal swaps” tend to result in relatively small changes in the placement cost， increasing their likelihood of acceptance. Initially， Dlimit is set to the entire chip. Whenever the temperature is reduced， the value of Dlimit is updated according to， and then clamped to the range 1 163。在不久的將來 VPR將支持緩沖和分段路由結(jié)構(gòu)，我們計(jì)劃增加定時(shí)分析儀和時(shí)序驅(qū)動(dòng)的路由。表 5還給出了大小每個(gè)邏輯塊的數(shù)量計(jì)算電路。列出三兩步（全球和詳細(xì)）路由與其它路由器進(jìn)行合并后的全球和詳細(xì)的路由。由于增加新的路徑路由的部分有一個(gè)零成本，由于這項(xiàng)新路徑通常相當(dāng)小迷宮路由器將首先擴(kuò)大它范圍，也需要相對較少的時(shí)間來添加此新波，如果整個(gè)波前擴(kuò)展了能實(shí)現(xiàn)那么下一個(gè)接收器 6 將達(dá)到的速度遠(yuǎn)遠(yuǎn)超過現(xiàn)在。對使用路由資源成本的函數(shù)，其對資源的任何過度使用都會(huì)讓當(dāng)前路由發(fā)生事先迭代。減少溫度每秒移動(dòng)數(shù)的 10倍，例如，加快安置到 10倍，并降低了大約只有 10％的最終填筑質(zhì)量。對于每一個(gè)網(wǎng)，北方新宇和 bby指出在其邊界框的水平和垂直跨度分別為 Q（ n）的因數(shù)補(bǔ)償。此外，如果全球路由要執(zhí)行，你也可以指定： ?橫向和縱向通道的相對寬 度之和 ?在不同區(qū)域的 FPGA的渠道相對寬度。 1 簡介 在 FPGA 的研究中，人們通常必須評估新結(jié)構(gòu)特色的實(shí)用工具而做評估實(shí)驗(yàn)。本文介紹了通用的地點(diǎn)和路線（ VPR）工具，設(shè)計(jì)很靈活，足夠讓許多 FPGA架構(gòu)的比較 VPR可以執(zhí)行的位置，要么全球路由或合并后的全球詳細(xì)路由。添加新的路由架構(gòu)的功能 VPR相對容易，因?yàn)?VPR使用體系結(jié)構(gòu)描述來創(chuàng)建路由資源圖。 Q是對總體 1有 3個(gè)或更少的終端，并慢慢增加了 50臺(tái)網(wǎng)邏輯與上 。有了這個(gè)動(dòng)機(jī)，我們提出了一個(gè)新的溫度更新附表，在溫度增加的時(shí)間花費(fèi)在一個(gè)重要的小區(qū)域上，但不是全部動(dòng)作都被接受。為了避免過于迂回路線以節(jié)省 CPU時(shí)間，我們讓一個(gè)去凈路由最外的 3 個(gè)通道的凈終端 邊界框。所得結(jié)果在本節(jié)獲得了邏輯的 4輸入 LUT加上一個(gè)觸發(fā)器組成的塊，如圖所示在圖 2。 VPR使用少于 13％資源數(shù)目的同時(shí)，它將執(zhí)行合并后的全球和詳細(xì)的路由，世嘉比用于執(zhí)行詳細(xì)路由對 AA VPR生成全版圖走線。由 VPR增加路由產(chǎn)生的全版圖航線曲目