【正文】 em, announced the VHDL of new edition, namely IEEE standard of 10761993 editions, .(call 93 versions)Now, VHDL and Verilog are the industrial standard hardware description of the IEEEs language, again arrive support of numerous EDA panies, at electronics engineering realm, have bee in general use hardware to describe language in is expert think, in the new century in, the VHDL will start to undertake a greatly part of numerical system design mission at the Verilog language. The VHDL language is a kind of deluxe language which useds for an electric circuit expects to appear after the 8039。Since the support mold piece turns a design, support layer39。例如在飛機(jī)制造過程中，從設(shè)計(jì)、性能測試及特性分析直到飛行模擬，都可能涉及到EDA 技術(shù)。因此它的應(yīng)用主要是應(yīng)用在數(shù)字電路的設(shè)計(jì)中。 VHDL 具有多層次的設(shè)計(jì)描述功能，既可 以描述系統(tǒng)級電路，又可以描述門級電路。符合市場需求的大規(guī)模系統(tǒng)高效， 高速的完成必須有多人甚至多個(gè)代發(fā)組共同并行工作才能實(shí)現(xiàn)。當(dāng)設(shè)計(jì)描述完成后，可以用多種不同的器件結(jié)構(gòu)來實(shí)現(xiàn)其功能。在對一個(gè)設(shè)計(jì)實(shí)體定義了外部界面后，一旦其內(nèi)部開發(fā)完成后，其他的設(shè)計(jì)就可以直接調(diào)用這個(gè)實(shí)體。 1987年底， VHDL 被 IEEE 和美國國防部確認(rèn)為標(biāo)準(zhǔn)硬件描述語言 。這一切極大地改變了傳統(tǒng)的數(shù)字系統(tǒng)設(shè)計(jì)方法、設(shè)計(jì)過程和設(shè)計(jì)觀念，促進(jìn)了 EDA 技術(shù)的迅速發(fā)展。 EDA的發(fā)展及 VHDL的應(yīng)用 9039。這些器件可以通過軟件編程而對其硬件結(jié)構(gòu)和工作方式進(jìn)行重構(gòu)，從而使得硬件的設(shè)計(jì)可以如同軟件設(shè)計(jì)那樣方便快捷。 VHDL 的英文全名是 VeryHighSpeed Integrated Circuit HardwareDescription Language,誕生于 1982年。 VHDL 的程序結(jié)構(gòu)特點(diǎn)是將一項(xiàng)工程設(shè)計(jì)，或稱設(shè)計(jì)實(shí)體（可以是一個(gè)元件，一個(gè)電路模塊或一個(gè)系 統(tǒng)）分成外部（或稱可是部分 ,及端口 )和內(nèi)部（或稱不可視部分），既涉及實(shí)體的內(nèi)部功能和算法完成部分。設(shè)計(jì)人員用 VHDL 進(jìn)行設(shè)計(jì)時(shí)，不需要首先考慮選擇完成設(shè)計(jì)的器件，就可以集中精力進(jìn)行設(shè)計(jì)的優(yōu)化。 （ 4）對于用 VHDL 完成的一個(gè)確定的設(shè)計(jì)，可以利用 EDA 工具進(jìn)行邏輯綜合和優(yōu)化，并自動(dòng)的把 VHDL描述設(shè)計(jì)轉(zhuǎn)變成門級網(wǎng)表。而描述既可以采用行為描述、寄存器傳輸描述或結(jié)構(gòu)描述，也可以采用三者混合的混合級描述。目前，它在中國的應(yīng)用多數(shù)是用在 FPGA/CPLD/EPLD 的設(shè)計(jì)中。本文所指的 EDA 技術(shù)，主要針對電子電路設(shè)計(jì)、 PCB 設(shè)計(jì)和 IC 設(shè)計(jì)。s turn a design again. Support extensively and be easy to a the VHDL has already bee IEEE standard the norm of hardware description language, most EDA tools almost support VHDL currently, this is VHDL of further expansion with extensively applied lay the design process of the hardware electric circuit, the main design document is the source code which writes with the VHDL, the VHDL easily reads with the structure turn, so be easy to a modification design. The strong system hardware describes VHDL has a multilayer design description function, since can describe system class electric circuit, can describe door class electric circuit description since can adopt a behavior description, deposit a machine to deliver description or structure description, can also adopt the hybrid description of threes , VHDL support is inertial to delay and deliver to delay, can also accurately build up hardware electric circuit support prepare definite of with from definition of data type, bring hardware description a bigger freedom degree, make design the personnel can expediently establish the system model of high time. The independence is at the design of spare part, have nothing to do with the 39。s in 20 centuries, calculator assistance manufacturing(CAM), calculator assistance test(CAT) and calculator lend support to the concept of engineering(CAE) a development since EDA technique is to take calculator as tool, design at EDA software terrace up, use the hardware description language HDL pleti